ANALOG DEVICES, INC.Download PDFPatent Trials and Appeals BoardNov 2, 202014911239 - (D) (P.T.A.B. Nov. 2, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/911,239 02/09/2016 MIKAEL MORTENSEN 05974.0008- NP (APD4956-2) 8892 110506 7590 11/02/2020 Patent Capital Group - Analog Attn: Shirley Fung 3267 E 3300 S #515 Salt Lake City, UT 84109 EXAMINER KRZYSTAN, ALEXANDER J ART UNIT PAPER NUMBER 2653 NOTIFICATION DATE DELIVERY MODE 11/02/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): PAIR_110506@patcapgroup.com bonnie@patcapgroup.com eofficeaction@appcoll.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MIKAEL MORTENSEN, MELISSA NOLET, and KHIEM QUANG NGUYEN Appeal 2019-003709 Application 14/911,239 Technology Center 2600 Before ALLEN R. MACDONALD, BRADLEY W. BAUMEISTER, and MICHAEL J. STRAUSS, Administrative Patent Judges. STRAUSS, Administrative Patent Judge. DECISION ON APPEAL1 STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the Examiner’s decision to reject claims 21, 23–37, 40–43. See Final Act. 1. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 We refer to the Specification, filed February 9, 2016 (“Spec.”); the Final Office Action, mailed March 8, 2018 (“Final Act.”); the Appeal Brief, filed August 13, 2018 as revised November 14, 2018 (“Appeal Br.”); the Examiner’s Answer, mailed February 7, 2019 (“Ans.”); the Examiner’s Supplemental Answer, mailed February 25, 2019 (“Supp. Ans.”); and the Reply Brief, filed April 8, 2019 (“Reply Br.”). 2 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Analog Devices, Inc. Appeal Br. 2. Appeal 2019-003709 Application 14/911,239 2 CLAIMED SUBJECT MATTER The claims are directed to low latency processing of digital data. Abstract. Claim 21, reproduced below with formatting altered including bracketed labels added and disputed limitation (d)(iii) emphasized in italics, is illustrative of the claimed subject matter: 21. A low latency communication system, comprising: [(a)] a first processing circuit to: [(b)] receive an input frame of digital data, wherein [(i)] the input frame includes a frame start signal followed by digital data arranged into time-divided data slots, [(ii)] the time-divided data slots include a last data slot and one or more other data slots, and [(iii)] the input frame of digital data is followed by another frame start signal indicating a start of another input frame, [(c)] perform a signal processing operation on the digital data in at least one other data slot to generate processed digital data, wherein the signal processing operation on the digital data in the at least one other data slot is initiated before the last data slot is received, and [(d)] [(i)] transmit the processed digital data in an output frame of digital data, wherein [(ii)] the output frame includes a frame start signal followed by the processed digital data arranged into time-divided data slots, and [(iii)] the frame start signal of the output frame is transmitted before the last data slot is received. REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Chennakeshu US 5,151,926 Sep. 29, 1992 Ookuri US 2012/0308022 A1 Dec. 6, 2012 Kessler US 2014/0025999 A1 Jan. 23, 2014 Appeal 2019-003709 Application 14/911,239 3 STATEMENT OF THE REJECTIONS3 Claims 21, 23, 24, 26–28, 37, and 40–43 stand rejected under 35 U.S.C. § 103 as being unpatentable over Chennakeshu and Kessler. Final Act. 3–7. Claims 25 and 29–36 stand rejected under 35 U.S.C. § 103 as being unpatentable over Chennakeshu, Kessler, and Ookuri. Final Act. 8–10. DETERMINATIONS AND CONTENTIONS The Examiner finds that Chennakeshu’s digital radio system receiver discloses most of the limitations of independent claim 21, including limitations (a), (b)(i), (b)(ii), (c), and (d)(i). Final Act. 3–4. The Examiner finds Kessler’s master slave microphone audio telephone system teaches limitations (b)(iii) and (c)(ii) in addition to disputed limitation (c)(iii) reciting the frame start signal of the output frame is transmitted before the last data slot is received. Id. at 4. The Examiner determines that the references’ teachings can be combined because “[the] processing and transmission of Chennakeshu could use synchronization response frames and superframes [(as taught by Kessler)] for the purpose of synchronizing the system, where the processing must all occur before the upstream transmission begins.” Id. In particular, the Examiner explains that, according to a first mapping of the references, 3 The Examiner initially also rejected claims 31 under 35 U.S.C. § 112, second paragraph, as failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention, but the Examiner subsequently withdrew this rejection. Cf. Final Act. 2 with Examiner’s Answer (Ans. 3). Appeal 2019-003709 Application 14/911,239 4 [Chennakeshu’s delay circuit] stage 32 receives the beginning samples from slot 1 of Fig. 2a (or whichever of slots 1–3 are received first), which is framed/defined in block 30 via blocks 15 and 120, including the indicator/start of the superframe taught by Kessler, and is processed (a signal processing operation being the delay process as applied to the samples within the slot 1), and then the processed slot 1 is output along with the superframe indicator before the next slot (slot 2) is received. The output frame is the superframe indicator along with slot 1 which is output before slot 2 or [slot 3 has] been received by the signal processing operation. The cited signal processing operations are on a slot synchronized basis as per Col 6 lines 25-35 which recites sample synchronization to a TDMA frame/slot (Chennakeshu). Id.at 11 (emphasis added). The Examiner finds Chennakeshu’s stages 13, 42, 52, and 76 similarly function to teach the emphasized temporal relationship wherein “[t]he output frame is the superframe indicator along with slot 1[,] which is output before slot 2 or [slot 3] have been received by the signal processing operation.” Id. at 12–16. Appellant contends, inter alia, Chennakeshu fails to teach the temporal relationship of limitation (d)(iii). Appeal Br. 7–8. According to Appellant, [N]o part of Chennakeshu indicates that these adjusted coefficients (Ik, Qk) are arranged into any particular kind of frame/slot format, nor does Chennakeshu or Kessler provide any rationale for arranging them into a frame/slot format and then utilizing Kessler’s alleged frame start signal to provide the adjusted coefficients (lk, Qk) to the delay circuit 32. Id. at 7. Appeal 2019-003709 Application 14/911,239 5 Appellant further argues The portion of Chennakeshu at col. 6, lines 25–35, cited in the Action, states only that “prior to establishing sample timing, it is necessary to synchronize to a TDMA frame/slot. This can be done using a correlation with the preamble sequence contained within each slot.” There is no teaching or suggestion in Chennakeshu that the delay circuit 32 need output any data before the data slots 2 or 3 are received by the system of FIG. 5. Further, no combination of Chennakeshu or Kessler provides any rationale for arranging the output of the delay circuit 32 into a frame/slot format along with Kessler’s alleged frame start signal. Thus, no combination of the references teaches or suggests to “transmit the processed digital data in an output frame of digital data, wherein the output frame includes a frame start signal followed by the processed digital data arranged into time-divided data slots, and the frame start signal of the output frame is transmitted before the last data slot is received,” in combination with the other limitations of claim 21. Id. at 7–8. In response, the Examiner further explains, [T]he TDMA framing structure disclosed in Chennakeshu Fig. 2 is used to provide synchronization in a TDMA system (Chennakeshu Col 2 lines 40-55). As such[,] all of the disclosed digital stages must conform to the stated protocol (the TDMA system) in order to synchronize[,] as disclosed by Chennakeshu. As such[,] the adjusted coefficients will be communicated to the rest of the system using the same TDMA framing structure, as well as any additional super framing (the cited synchronization control frame) taught by Kessler, in order to synchronize the different processing stages of the device. Ans. 5; Supp. Ans. 5–6. The Examiner further finds, The framing protocol defines the blocks of data [that] are processed by each stage in fig. 5 of Chennakeshu. The first Appeal 2019-003709 Application 14/911,239 6 frame/slot of Chennakeshu will complete processing by a stage 32 in fig. 5 because that is how the framing is defined in fig, 2. The addition of a superframe indicator/SCF as taught by Kessler will be output (with the control signaling of the first slot of Chennakeshu) after the first slot is processed by stage 32, in order for the next slot to be processed where the next slot will not contain the SCF taught by Kessler because the superframes of Kessler by definition comprise more than one frame/slot. Ans. 5–6, Supp. Ans. 6. Appellant replies, arguing, The purpose of the detector of Chennakeshu’s FIG. 5 is to take an incoming IF signal and properly decode it. There is no support for the assertion that data generated internal to the detector is re- encoded after each operation into a TDMA format, and then decoded before the next operation. Reply Br. 3. STANDARD OF REVIEW The Board conducts a limited de novo review of the appealed rejections for error based upon the issues identified by Appellant, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). ANALYSIS Appellant’s contentions are persuasive of reversible Examiner error. In particular, the Examiner has not established in any of the proposed mappings of the claim language to the cited references that the combination of Chennakeshu and Kessler teaches or suggests disputed limitation (d)(iii) requiring the frame start signal of the output frame is transmitted before the Appeal 2019-003709 Application 14/911,239 7 last data slot is received. In particular, the Examiner has not established that either Chennakeshu or Kessler discloses the recited temporal relationship between processing performed within Chennakeshu’s receiver and the Synchronization Control Frame (SCF) of Kessler’s superframes. And we find insufficient evidence to support the Examiner’s finding that Chennakeshu’s stage 32 will complete processing of a first frame/slot in any particular timing relation to other events such as receipt of a last data slot or that a frame start signal of an output frame would be transmitted before the last data slot is received. See Ans. 5–6. Furthermore, the Examiner provides insufficient evidence to support the stated rationale for why the recited temporal relationship necessarily would be present in the asserted combination. That is, we find insufficient evidence that, even if Chennakeshu were modified to adopt Kessler’s superframe structure, the combination would teach or suggest the particular configuration advanced by the Examiner including use of a superframe structure at the input and output of each processing stage of Chennakeshu’s receiver. See id. at 5. In particular, the combination of Chennakeshu and Kessler fails to teach internally decoding and encoding a data signal from/into a superframe format when transmitting a data signal within a particular device and, in particular, a receiver providing an analog output signal such as Chennakeshu’s receiver. Thus, we find insufficient evidence to support the Examiner’s finding that “adjusted coefficients will be communicated to the rest of [Chennakeshu’s] system using the same TDMA framing structure . . . to synchronize the different processing stages [of Chennakeshu’s] device.” Appeal 2019-003709 Application 14/911,239 8 Because we agree with at least one of the arguments advanced by Appellant, we need not reach the merits of Appellant’s other arguments. Accordingly, we do not sustain the rejection of independent claim 21 under 35 U.S.C. § 103 or, for the same reasons, the rejection of independent claim 37, which includes similar limitations, or the rejection of claims 23, 24, 26–28, 40–43, which depend from these independent claims. With respect to the additional obviousness rejection of dependent claims 25 and 29–36, the Examiner does not rely on the additionally cited reference, Ookuri, to cure the deficiency of the obviousness rejection of claim 21, noted above. Final Act. 8–10. Accordingly, we do not sustain this rejection for the same reasons noted above. DECISION Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 21, 23, 24, 26–28, 37, 40–43 103(a) Chennakeshu, Kessler 21, 23, 24, 26–28, 37, 40–43 25, 29–36 103(a) Chennakeshu, Kessler, Ookuri 25, 29–36 Overall Outcome 21, 23–37, 40–43 REVERSED Copy with citationCopy as parenthetical citation