Amer, Ihab et al.Download PDFPatent Trials and Appeals BoardMay 15, 20202019005393 (P.T.A.B. May. 15, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/085,562 03/30/2016 Ihab Amer AMDI:319\HON 6923 16501 7590 05/15/2020 Timothy M. Honeycutt Attorney at Law 37713 Parkway Oaks Ln. Magnolia, TX 77355 EXAMINER DANG, PHILIP ART UNIT PAPER NUMBER 2488 NOTIFICATION DATE DELIVERY MODE 05/15/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): elizabethahoneycutt@earthlink.net timhoney@sprynet.com timhoneycutt@earthlink.net PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte IHAB AMER, GABOR SINES, KHALED MAMMOU, HAIBO LIU, and ARUN SUNDARESAN IYER Appeal 2019-005393 Application 15/085,562 Technology Center 2400 Before JAMES R. HUGHES, JOYCE CRAIG, and MATTHEW J. McNEILL, Administrative Patent Judges. CRAIG, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–21. See Final Act. 6–37. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Advanced Micro Devices, Inc. Appeal Br. 1. Appeal 2019-005393 Application 15/085,562 2 CLAIMED SUBJECT MATTER The claims are directed to video processing. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A method of processing video data, comprising: encoding or decoding the video data with a codec in aggressive deployment; and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re- decoding the video data in a non-aggressive deployment or generating a skip picture. REJECTIONS2 Claims 1–3, 8–10, and 15–17 stand rejected under 35 U.S.C. § 103 as unpatentable over the combination of Papanikolaou et al. (US 8,037,430 B2; issued Oct. 11, 2011) (“Papanikolaou”) and Eleftheriadis et al. (US 8,436,889 B2; issued May 7, 2013) (“Eleftheriadis”). Final Act. 6–18. Claims 4, 11, and 18 stand rejected under 35 U.S.C. § 103 as unpatentable over the combination of Papanikolaou, Eleftheriadis, and Smith et al. (US 9,226,193 B2; issued Dec. 29, 2015) (“Smith”). Final Act. 18–22. Claims 5, 12, and 19 stand rejected under 35 U.S.C. § 103 as unpatentable over the combination of Papanikolaou, Eleftheriadis, and Dare et al. (US 8,615,581 B2; issued Dec. 24, 2013) (“Dare”). Final Act. 22–28. 2 Although there is no outstanding rejection under 35 U.S.C. § 101, the Examiner may wish to consider whether, in accordance with the USPTO’s 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (Jan. 7, 2019), the claims are directed to a judicial exception without significantly more. Specifically, in RecogniCorp, LLC v. Nintendo Co., Ltd., the Federal Circuit found patent-ineligible a claim “directed to the abstract idea of encoding and decoding image data.” 855 F.3d 1322, 1326 (Fed. Cir. 2017). Appeal 2019-005393 Application 15/085,562 3 Claims 6, 7, 13, 14, 20, and 21 stand rejected under 35 U.S.C. § 103 as unpatentable over the combination of Papanikolaou, Eleftheriadis, and Vaidyanathan (US 7,010,030; issued Mar. 7, 2006). Final Act. 28–37. ANALYSIS With respect to independent claim 1, Appellant contends the Examiner erred because Papanikolaou does not teach or suggest “encoding or decoding the video data with a codec in aggressive deployment.” See Appeal Br. 15– 17; Reply Br. 1–2. In particular, Appellant proposes construing “aggressive deployment” according to the alleged definition in paragraph 27 of the Specification, which “includes voltage and/or frequency moved out of their worst case ranges.” Reply Br. 2–3. We differ with Appellant regarding the proper construction of “aggressive deployment,” but, nevertheless, Appellant’s argument persuades us that the Examiner erred. The Specification discloses that “[a]ggressive deployment (or better- than-worst-case) is a low power design trend, which suggests operating a digital circuit on a voltage level that is lower than its qualified minimum, and detecting/correcting the statistically-rare errors that may occur in the circuit.” Spec. ¶ 5. The Specification elaborates as follows: Aggressive deployment is also known as “Better-than-worst- case (BTWC) design.” As noted above in the Background section, in worst case designs, driving voltage and clock frequency are limited to ranges which allow the circuit in question to function normally even though all component values simultaneously assume the worst possible condition that can be cause by process variations, temperature, critical path considerations, circuit age, etc. . . . However, during aggressive deployment, the voltage Vreg73 and/or the frequency f73 may be moved out of the worst case ranges. Appeal 2019-005393 Application 15/085,562 4 Spec. ¶ 27. In light of the above disclosure, we construe “aggressive deployment” to mean operating a circuit with a parameter value outside of a worst-case range that assumes the worst possible operating conditions. We do not import limitations into claim 1, such as requiring either voltage or frequency to operate below or above a worst case design limit, because the Specification provides these operating states as merely exemplary. For example, the Specification discloses “Vreg73 may be lowered below Vworstcaselow and the frequency f73 may be kept at some steady value fworstcaselow< f73< fworstcasehigh,” or, “[i]n another option that represents a boost mode, i.e., an overclocking mode, the frequency f73 may be raised above fworstcasehigh while Vreg73 is kept within VworstcaselowCopy with citationCopy as parenthetical citation