Ambiq Micro, Inc.

Patent Trials and Appeals Board

Feb 23, 2022

2021002401 (P.T.A.B. Feb. 23, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/648,298 07/12/2017 Christophe J. Chevallier AMBQ-00100 3183 34051 7590 02/23/2022 Stevens Law Group 1754 Technology Dr. Ste 226 San Jose, CA 95110 EXAMINER HUANG, MIN ART UNIT PAPER NUMBER 2827 NOTIFICATION DATE DELIVERY MODE 02/23/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): uspto@stevenslawgroup.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ___________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ___________ Ex parte CHRISTOPHE J. CHEVALLIER ___________ Appeal 2021-002401 Application 15/648,298 Technology Center 2800 ___________ Before GEORGE C. BEST, CHRISTOPHER C. KENNEDY, and JANE E. INGLESE, Administrative Patent Judges. BEST, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1-20 and 26-29 of Application 15/648,298. Non-Final Act. (November 27, 2019). Because at least one of the claims on appeal has been twice rejected, we have jurisdiction under 35 U.S.C. § 6. For the reasons set forth below, we affirm in part. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Ambiq Micro, Inc. as the real party in interest. Appeal Br. 3. Appeal 2021-002401 Application 15/648,298 2 I. BACKGROUND The ’298 Application describes a static random access memory (SRAM) circuit with reduced power usage. Spec. ¶ 1. SRAM circuits are used to store digital information in a variety of mobile and hand-held devices. Id. ¶ 2. SRAM circuits require substantially continuous power for operation, making efficient power usage a key concern. Id. Claim 1 is representative of the ’298 Application’s claims and is reproduced below from the Appeal Brief’s Claims Appendix. We have italicized the limitations that are important to this appeal. 1. A SRAM circuit comprising: arrays of SRAM bit cells, each capable of storing a bit of information, that together define an address bitmap, each array of the arrays of SRAM bit cells including a sense amplifier and a write driver; peripheral circuitry able to generate selected control, data, and address signals, connected to the arrays of SRAM bit cells and positioned at a designated location, the peripheral circuitry including at least one array decoder for each array of the arrays of SRAM bit cells located at the designated location and signal lines coupling the at least one array decoder to the sense amplifier and the write driver of the each array, the sense amplifier and the write driver of each array of the arrays of SRAM bit cells not being at the designated location and being adjacent the arrays of SRAM bit cells; and wherein a subset of arrays in the arrays of SRAM bit cells are mapped to a subset of the address bitmap, and are placed adjacent to the designated location. Appeal Br. 16 (emphasis added). Appeal 2021-002401 Application 15/648,298 3 II. REJECTIONS On appeal, the Examiner maintains2 the following rejections: 1. Claims 1, 4, and 5 are rejected under 35 U.S.C. § 102(a)(1) as anticipated by Morishima.3 Non-Final Act. 5. 2. Claims 2, 3, 6, and 9 are rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima and Mueller.4 Non-Final Act. 6. 3. Claims 7 and 8 are rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima and Hess.5 Non-Final Act. 7. 4. Claims 10-13 are rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima and Noguchi.6 Non-Final Act. 8. 5. Claims 14-20, 28, and 29 are rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima, Noguchi, and Mueller. Non-Final Act. 9. 6. Claim 26 is rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima, Noguchi, Mueller, and Hess. Non-Final Act. 10. 2 The Examiner has withdrawn the rejection of claims 1-10 as indefinite. Answer 3. 3 US 2006/0023555 A1, published February 2, 2006. 4 US 5,923,605, issued July 13, 1999. 5 US 2016/0071574 A1, published March 10, 2016. 6 US 2017/0053689 A1, published February 23, 2017. (Cont’d) Appeal 2021-002401 Application 15/648,298 4 7. Claim 27 is rejected under 35 U.S.C. § 103 as unpatentable over the combination of Morishima, Noguchi, Mueller, Hess, and Tsuruta.7 Non-Final Act. 11. III. DISCUSSION A. Rejection of claims 1, 4, and 5 as anticipated by Morishima Appellant argues for reversal of this rejection based upon the limitations of independent claim 1. Appeal Br. 7-10. We, therefore, select claim 1 as representative of the claims subject to this rejection and limit our discussion accordingly. 37 C.F.R. § 41.37(c)(1)(iv) (2019). Claim 1 requires a portion of the circuitry used to operate a plurality of ceramic bit cells to be located at a “designated location.” The array decoder for each of the bit seller arrays is one type of circuitry that is to be so located. Claim 1 further specifies that the sense amplifier and the write driver circuits are located adjacent to the array of bit cells and not at the “designated location.” 7 US 2014/0191328 A1, published July 10, 2014. Appeal 2021-002401 Application 15/648,298 5 In rejecting claim 1, the Examiner found that Morishima’s Figures 4 and 5 depict such an arrangement. Non-Final Act. 5. For ease of reference, we reproduce Morishima’s Figure 4 below. Morishima’s Figure 4 is a schematic diagram of an IO block. Morishima ¶ 34. The Examiner specifically found that control circuit CTL, row decode circuits XD, and circuits LC correspond to the claimed peripheral circuitry positioned at a “designated location.” Non-Final Act. 5. The Examiner also found that each column circuit YC corresponds to the recited sense amplifier and write driver located adjacent to the array rather than at the “designated location.” Id. In making this determination, the Examiner stated that “the location of CTL, XD and LC is considered to be the ‘designated location’. A designated location is the area in which the circuits are located.” Answer 3. Appeal 2021-002401 Application 15/648,298 6 Appellant argues that the Examiner erred because Morishima’s Figure 4 shows row decode circuits XD as adjacent to the arrays rather than being co-located with the control circuit CTL at the designated location. Appeal Br. 8-9; Reply Br. 3 (“The control circuit (CTL) and row decode circuit (XD) are both characterized as being at the same designated location when this is not the case.”). We begin by determining the proper interpretation of the claim term “designated location.” During prosecution, we give the language of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account any definitions or other enlightenment provided by the written description contained in the applicant’s specification. In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). We first consider the meaning of the adjective “designated.” “Designated” is the past participle of the verb “designate.” In the context provided by the ’298 Application’s Specification, the ordinary meaning of the verb “designate” is “to indicate and set apart for a specific purpose.” Designate Definition & Meaning - Merriam-Webster, Merriam- Webster.com, https://www.merriam-webster.com/dictionary/designate. Next, we consider the meaning of the noun “location.” In the context provided by the Specification, the ordinary meaning of “location” is “an area designated for a purpose.” See, e.g., Location Definition & Meaning - Merriam-Webster, Merriam-Webster.com, https://www.merriam- webster.com/dictionary/location (defining “location” as “a tract of land designated for a purpose”). Appeal 2021-002401 Application 15/648,298 7 In this context, therefore, the broadest reasonable interpretation of the phrase “designated location” is “an area set aside for a specific purpose.” Claim 1 sets forth the purpose of the designated location. According to claim 1, the designated location is where the “peripheral circuitry able to generate selected control, data and address signals . . . including at least one array decoder for each array of the arrays of SRAM bit cells” is positioned. Appeal Br. 16. Moreover, the Specification makes it clear that the “designated location” is an area where all of the peripheral circuitry identified in the claim is grouped together. See, e.g., Spec. ¶¶ 25, 35; Fig. 5. The Examiner, however, appears to have interpreted the phrase “designated location” more broadly than the definition given above. See, e.g., Answer 3. In particular, the Examiner appears to have interpreted claim 1 as not requiring co-location of all the peripheral circuitry. Id. The Examiner’s interpretation effectively removes the limitation from the claims and is inconsistent with the Specification. In re Smith Int’l, Inc., 871 F.3d 1375, 1382-83 (Fed. Cir. 2017) (“The correct inquiry in giving a claim term its broadest reasonable interpretation in light of the specification is not whether the specification proscribes or precludes some broad reading of the claim term adopted by the examiner. And it is not simply an interpretation that is not inconsistent with the specification. It is an interpretation that corresponds with what and how the inventor describes his invention in the specification, i.e., an interpretation that is consistent with the specification.” (internal quotation omitted)). Having construed the relevant portion of claim 1, we are persuaded by Appellant’s argument. Morishima’s Figure 4 does not describe colocation of all the depicted peripheral circuitry. See Appeal Br. 8-9. Specifically, the Appeal 2021-002401 Application 15/648,298 8 row decoder circuits XD are shown adjacent to the cell arrays rather than being at the designated location with control circuitry CTL. Thus, we reverse the rejection of claim 1 as anticipated by Morishima. Accordingly, we also reverse the rejection of claims 4 and 5, which depend from claim 1. B. Rejection of claims 2, 3, 6, and 9 as unpatentable over the combination of Morishima and Mueller Claims 2, 3, 6, and 9 depend from claim 1. See Appeal Br. 16-17. In rejecting these claims, the Examiner relies upon Morishima as describing all of the limitations in claim 1. Non-Final Act. 6. As discussed above, we have determined that this finding is erroneous because Morishima does not describe placing all of the components of the peripheral circuitry in the designated location. In rejecting claims 2, 3, 6, and 9, the Examiner does not establish that Mueller describes or suggests placing all of the components designated in claim 1 as peripheral circuitry at a designated location. On this record, therefore, we must reverse this rejection. C. Rejection of claims 7 and 8 as unpatentable over the combination of Morishima and Hess Claims 7 and 8 depend from claim 1. See Appeal Br. 17. In rejecting these claims, the Examiner relies upon Morishima as describing every limitation set forth in claim 1. Non-Final Act. 7. For the reasons set forth in § III.A, above, we have determined that Morishima does not describe every limitation of claim 1. In rejecting claims 7 and 8, the Examiner did not find that Hess describes or suggests co-location of all the peripheral circuitry at a designated location. Non-Final Act. 7. We, therefore, reverse the rejection of Appeal 2021-002401 Application 15/648,298 9 claims 7 and 8 for essentially the same reasons we reversed the rejection of claim 1. Moreover, the Examiner relies upon Hess as describing the limitations added by claims 7 and 8. Id. With respect to claim 7, the Examiner concedes that Hess’s array decoder is in a different power domain from the rest of the peripheral circuitry. Answer 4. This is inconsistent with the limitation of claim 1 which require the array decoder to be located at the same designated location as the rest of the peripheral circuitry. See claim 1 (“the peripheral circuitry including at least one array decoder . . . located at the designated location”). This provides an additional reason for reversing the rejection of claim 7. With respect to claim 8, we agree with Appellant’s argument that Hess does not describe address patent facilities and data path facilities in different power domains. See Reply Br. 5-6. This provides an additional reason to reverse the rejection of claim 8. D. Rejection of claims 10-13 as unpatentable over the combination of Morishima and Noguchi Claim 10 depends from claim 1. See Appeal Br. 17. Claim 11 is an independent claim. See id. at 18. Claims 12 and 13 depend from claim 11. See id. We, therefore, divide the claims subject to this rejection into two groups: (1) claim 10, and (2) claims 11-13. We discuss each group of claims separately. 1. Claim 10 In rejecting claim 10, the Examiner relies upon Morishima as describing every limitation of claim 1. Non-Final Act. 8. Appeal 2021-002401 Application 15/648,298 10 As discussed in § III.A, above, we have determined that Morishima does not describe every limitation of claim 1. In rejecting claim 10, the Examiner did not find that Noguchi describes or suggests colocation of all of the peripheral circuitry identified in claim 1. Because the Examiner did not find that Noguchi cures the deficiencies in the rejection of claim 1 as anticipated by Morishima, we also reverse the rejection of claim 10. 2. Claims 11-13 Claim 11 is independent. Appeal Br. 18. Claims 12 and 13 depend from claim 11. Id. We select claim 11 to represent this group of claims, 37 C.F.R. § 41.37(c)(1)(iv), and limit our discussion accordingly. For ease of reference, we reproduce independent claim 11 below. 11. An array control circuit connected to a plurality of array blocks comprising: peripheral circuitry connected by signal lines to the plurality of array blocks to access a subset of array blocks during an operation, the peripheral circuitry being positioned at a designated location, with an array decoder for each block of the plurality of array blocks being located at the designated location and sense amplifiers and write drivers for each block of the plurality of array blocks not being locate [sic] at the designated location; and wherein only those signal lines connecting the peripheral circuitry to the accessed subset of array blocks are active during the operation. Appeal Br. 18 (emphasis added). In rejecting claim 11, the Examiner relies upon Morishima as describing an array control circuit with peripheral circuitry including an array decoder for each block of the plurality of array blocks co-located at a Appeal 2021-002401 Application 15/648,298 11 designated location. Non-Final Act. 8-9 (citing Morishima Fig. 4). As we discussed in § III.A, we determine that Morishima describes array decoders that are adjacent to each of array blocks rather than being in the designated location. We, therefore, reverse the rejection of claim 11. Accordingly, we also reverse the rejection of claims 12 and 13. E. Rejection of claims 14-20, 28, 29 as unpatentable over the combination of Morishima, Noguchi, and Mueller Claims 14-19 and 29 depend from claim 11. See Appeal Br. 18-20. Claim 20 is an independent claim, and claim 28 depends from claim 20. See id. at 19-20. Thus, we divide the claims subject to this ground of rejection into two groups: (1) claims 14-19 and 29, and (2) claims 20 and 28. We discuss each group of claims separately. 1. Claims 14-19 and 29 Claims 14-19 and 29 depend from claim 1. See Appeal Br. 16-17. In rejecting these claims, the Examiner relies upon Morishima as describing all of the limitations in claim 1. Non-Final Act. 6. As discussed above, we have determined that this finding is erroneous because Morishima does not describe placing all of the components of the peripheral circuitry in the designated location. In rejecting claims 14-19 and 29, the Examiner does not establish that either Mueller or Noguchi describes or suggests placing all of the components designated in claim 11 as peripheral circuitry at a designated location. On this record, therefore, we must reverse this rejection. Appeal 2021-002401 Application 15/648,298 12 2. Claims 20 and 28 Claim 20 is independent. Appeal Br. 19. Claim 28 depends from claim 20. Id. We select claim 20 to represent this group of claims, 37 C.F.R. § 41.37(c)(1)(iv), and limit our discussion accordingly. For ease of reference, we reproduce independent claim 20 below. 20. A system with multiple arrays that can be selectively accessed, comprising: first circuitry positioned adjacent to at least some of the multiple arrays, the multiple arrays accessible and controllable with one or more control signals, and with only circuitry connected to access to raise being enabled, where in the first circuitry is sense amplifiers and write drivers; and second circuitry generating at least some of the one or more control signals to enable the first circuitry, the second circuitry being at a designated location and a center of the multiple arrays and including array decoder for the multiple arrays, the first circuitry not being at the designated location. Appeal Br. 19 (emphasis added). Appellant argues that the rejection of claim 20 should be reversed “for at least some of the reasons noted with respect to claim 1.” Id. at 14. This argument is not persuasive. In rejecting claim 20, the Examiner found that Morishima describes the claimed second circuitry including array decoder for the multiple arrays. Non-Final Act. 10 (citing Morishima Fig. 4). The Examiner further found that Mueller describes locating the second/control circuitry at a designated location at a center of the multiple arrays. Id. (citing Mueller Fig. 2). Thus, Appellant’s assertion that Mueller’s disclosure does not remedy Morishima’s deficiencies, see Appeal Br. 14, is incorrect. We, therefore, Appeal 2021-002401 Application 15/648,298 13 affirm the rejection of claim 20 over the combination of Morishima, Noguchi, and Mueller. Claim 28 is alleged to be patentable by virtue of its dependence from claim 20. Id. Because we have affirmed the rejection of claim 20, we also affirm the rejection of claim 28. F. Rejection of claim 26 as unpatentable over the combination of Morishima, Noguchi, Mueller, and Hess Claim 26 depends from claim 20. See Appeal Br. 20. For ease of reference, we reproduce claim 26 below. 26. The system of claim 20, wherein the multiple arrays and the second circuitry are in different power domains. Id. As we discussed in § III.E, the combination of Morishima, Noguchi, and Mueller describes or suggests every limitation in claim 20. The Examiner finds that Hess teaches the additional limitation recited in claim 26. Non-Final Act. 10. Hess’s Figure 1, however, shows that the array decoders are separated from the rest of the second circuitry as defined by claim 20 and are located adjacent to and in the same power domains as the memory arrays. Hess’s description, therefore, is inconsistent with the structure described or suggested by the combination of Morishima, Noguchi, and Mueller. The Examiner does not explain how or why a person having ordinary skill in the art at the time of the invention would have reconciled the structural differences between the systems described or suggested by the combination of Morishima, Noguchi, and Mueller and that described by Hess. On this record, therefore, we reverse the rejection of claim 26 as Appeal 2021-002401 Application 15/648,298 14 unpatentable over the combination of Morishima, Noguchi, Mueller, and Hess. G. Rejection of claim 27 as unpatentable over the combination of Morishima, Noguchi, Mueller, Hess, and Tsuruta Claim 27 depends from claim 26. See Appeal Br. 20. In rejecting claim 27, the Examiner did not find that Tsuruta remedies the deficiencies we identified in the rejection of claim 26. We, therefore, also reverse the rejection of claim 27. IV. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 4, 5 102(a)(1) Morishima 1, 4, 5 2, 3, 6, 9 103 Morishima, Mueller 2, 3, 6, 9 7, 8 103 Morishima, Hess 7, 8 10-13 103 Morishima, Noguchi 10-13 14-20, 28, 29 103 Morishima, Noguchi, Mueller 20, 28 14-19, 29 26 103 Morishima, Noguchi, Mueller, Hess 26 27 103 Morishima, Noguchi, Mueller, Hess, Tsuruta 27 Overall Outcome 20, 28 1-19, 26, 27, 29 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv) (2019). AFFIRMED IN PART