ACQIS LLC

Patent Trials and Appeals Board

Sep 14, 2021

IPR2021-00667 (P.T.A.B. Sep. 14, 2021)

Trials@uspto.gov Paper 8
571-272-7822 Date: September 14, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

SAMSUNG ELECTRONICS CO., LTD. and
SAMSUNG ELECTRONICS AMERICA, INC.,
Petitioner,
v.
ACQIS LLC,
Patent Owner.

IPR2021-00667
Patent 8,977,797 B2

Before THU A. DANG, JONI Y. CHANG, and SCOTT A. DANIELS,
Administrative Patent Judges.

DANIELS, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
35 U.S.C. § 314

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I. INTRODUCTION
Samsung Electronics Co., Ltd. and Samsung Electronics America,
Inc. (“Petitioner”), filed a Petition requesting inter partes review of claims
challenge claims 1–23 and 27–38 of U.S. Patent No. 8,977,797 B2
(Ex. 1001, “the ’797 patent”). Paper 3 (“Pet.”). ACQIS LLC (“Patent
Owner”), filed a Preliminary Response to the Petition. Paper 7 (“Prelim.
Resp.”).
Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
“unless . . . there is a reasonable likelihood that the petitioner would prevail
with respect to at least 1 of the claims challenged in the petition.” Upon
consideration of the arguments and evidence presented by Petitioner and
Patent Owner, we are not persuaded that Petitioner has demonstrated, under
35 U.S.C. § 314(a), a reasonable likelihood that it would prevail in showing
the unpatentability of at least one of the challenged claims of the ’797
patent. Accordingly, we decline to institute an inter partes review of the
challenged claims.
A. Real Parties in Interest
Petitioner states that the real parties-in-interest are Samsung
Electronics Co., Ltd. and Samsung Electronics America, Inc. Pet. 1. Patent
Owner states that ACQIS LLC is the real party-in-interest. Paper 5, 1.
B. Related Matters
The parties indicate that the ’797 patent has been asserted against
Petitioner in ACQIS LLC v. Samsung Electronics Co., Ltd., et al., Case No.
2:20-cv-00295-JRG in the United States District Court for the Eastern
District of Texas (the “Texas action”). Pet. 1; Prelim. Resp. 2; Paper 5, 1.
The ’797 patent is also challenged in IPR2021-00606 and Patent
Owner also identifies the following reexamination proceedings involving
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patents in the ’797 patent priority chain: Reexamination proceeding
95/001,276; Reexamination proceeding 95/001,310; Reexamination
proceeding 95/001,424; Reexamination proceeding 95/001,475; and
Reexamination proceeding 95/001,787. Pet. 1–2; Paper 5, 3.
C. The ’797 Patent (Ex. 1001)
The ’797 patent relates “to an interface channel that interfaces two
computer interface buses that operate under protocols that are different from
that used by the interface channel.” Ex. 1001, 3:8–12. The ’797 patent
more specifically describes that
[i]n one embodiment, the first and second interface controllers
comprise a host interface controller (HIC) and a peripheral
interface controller (PIC), respectively, the first and second
computer interface buses comprise a primary PCI and a
secondary PCI bus, respectively, and the interface channel
comprises an LVDS [(Low Voltage Differential Signal)]
channel.
Id. at 5:27–32.
Figure 6 of the ’797 patent, reproduced below with Petitioner’s
annotations, provides a diagram of a computer system using an exchange
interface system referred to as “XIS Bus” 615, including interface channel
“XP Bus” 618. Ex. 1001, 15:22–24.
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Annotated Figure 6 above illustrates a block diagram of computer system
600 using XIS Bus interface 615. Id. at 15:15−16. As shown, computer
system 600 includes attached computer module (ACM) 605 and peripheral
console 610. Id. at 15:16−18. ACM 605 and peripheral console 610 are
interfaced through exchange interface system XIS Bus 615. Id. at 15:23−24.
XIS Bus 615 includes power bus 616, video bus 617 and interface channel
XP Bus 618. Id. at 15:24−27.
The lines of XP Bus may be low voltage differential signal (LVDS)
lines that transmit fixed length data packets within a clock cycle. Id. at
22:26–28. More particularly, the ’797 patent describes that XP Bus includes
bit “lines PCK, PD0 to PD3, and PCN” which “are unidirectional LVDS
lines for transmitting clock signals and bits.” Id. at 21:60–62. The ’797
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patent explains that “[a] bit based line (i.e., a bit line) is a line for
transmitting serial bits. Bit based lines typically transmit bit packets and use
a serial data packet protocol. Examples of bit lines include an LVDS line,
an IEEE 1394 line, and a Universal Serial Bus (USB) line.” Id. at 22:51–55.
According to the ’747 patent, the benefit of interface channel XP Bus using
LVDS line is that “[t]his reduces the number of physical signal paths
required to traverse the interconnection 1900. Further, employing low-
voltage differential signaling (LVDS) on the bit stream data paths provides
very reliable, high-speed transmission across cables.” Id. at 24:38–42.
Figure 10 reproduced below, as annotated by the Board, details how
signals from Host PCI Bus are encoded as bits by encoder 627, then
converted from parallel to serial data transmission before being handed by
LVDS bit lines PD0 to PD3 to XP Bus.
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Annotated Figure 10 above illustrates the conversion of Host PCI data
signals to bits, and parallel to serial conversion prior to transmission by XP
Bus to Secondary PCI Bus (not shown). Id. at 17:1–65.
D. Illustrative Claim
Of the challenged claims, claims 1, 4, 7, 10, 14, 18, 21, 27, 30, 33, and
36 are independent. Among the dependent claims, claims 2 and 3 depend
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from claim 1, claims 5 and 6 depend from claim 4, claims 8 and 9 depend
from claim 7, claims 11–13 depend from claim 10, claims 15–17 depend
from claim 14, claims 19 and 20 depend from claim 18, claims 22 and 23
depend from claim 21, claims 28 and 29 depend from claim 27, claims 31
and 32 depend from claim 30, claims 34 and 35 depend from claim 33, and
claims 37 and 38 depend from claim 36.
Independent claim 4 is reproduced below, with certain limitations of
interest highlighted, and is illustrative of the claimed subject matter:1
4. [a] A method of improving computer peripheral data
communications, comprising:
[b] mounting a Central Processing Unit (CPU) on a
printed circuit board of a computer system;
[c] connecting a Low Voltage Differential Signal (LVDS)
channel directly to the CPU on the printed circuit board, the
LVDS channel comprising two unidirectional, serial channels
that transmit data in opposite directions;
[d] increasing data throughput of the serial channels by
providing each channel with multiple pairs of differential signal
lines;
[e] conveying encoded address and data bits of a
Peripheral Component Interconnect (PCI) bus transaction in
serial form over the serial channels to preserve the PCI bus
transaction;
[f] coupling the CPU to a peripheral device through the
LVDS channel; and
[g] applying power to the computer system.
Ex. 1001, 38:17–34.

1 We reference Petitioner’s labels [a]-[g] in claim 4. See Pet. 20–31.
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E. Prior Art and Asserted Grounds
Petitioner asserts that claims 1–23 and 27–38 would have been
unpatentable on the following grounds:2

Claim(s)
Challenged
35 U.S.C. § Reference(s)/Basis
1 4–6, 14–17, 21–23,
36–38
103(a)3 Gulick,4 Goodrum5
2
27–31, 33, 34 103(a)
Gulick, Goodrum,
McAlear6
3 7–9, 18–20 103(a) Hart,7 Goodrum
4 1–3, 10–13 103(a) Hart, Goodrum, McAlear
5
32, 35 103(a)
Gulick, Goodrum,
McAlear, Sauber8
II. ANALYSIS
A. Claim Construction
We interpret a claim “using the same claim construction standard that
would be used to construe the claim in a civil action under 35 U.S.C.
282(b).” 37 C.F.R. § 42.100(b). Under this standard, we construe the claim
“in accordance with the ordinary and customary meaning of such claim as

2 Petitioner supports its challenge with a Declaration of Dr. Stephen A.
Edwards (Ex. 1003) and Patent Owner relies upon the Declaration of Dr.
Marc. E. Levitt (Ex. 2001). See infra.
3 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
Stat. 284, 287–88 (2011), amended 35 U.S.C. § 103, effective March 16,
2013. Because the application from which the ’797 patent issued has an
effective filing date prior to March 16, 2013, the pre-AIA version of § 103
applies. See Ex. 1001, codes (22) and (63).
4 Ex. 1004, U.S. Patent No. 6,690,676 B1 (iss. Feb. 10, 2004).
5 Ex. 1006, U.S. Patent No. 5,822,571 (iss. Oct. 13, 1998).
6 Ex. 1007, U.S. Patent No. 6,389,029 B1 (iss. May 14, 2002).
7 Ex. 1008, U.S. Patent No. 6,041,372 (iss. Mar. 21, 2000).
8 Ex. 1009, U.S. Patent No. 6,600,747 B1 (iss. July 29, 2003).
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understood by one of ordinary skill in the art and the prosecution history
pertaining to the patent.” Id. Furthermore, at this stage in the proceeding,
we expressly construe the claims only to the extent necessary to determine
whether to institute inter partes review. See Nidec Motor Corp. v.
Zhongshan Broad Ocean Motor Co. Ltd., 868 F.3d 1013, 1017 (Fed. Cir.
2017) (“[W]e need only construe terms ‘that are in controversy, and only to
the extent necessary to resolve the controversy.’” (quoting Vivid Techs., Inc.
v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
1. “peripheral bridge”
Petitioner contends that a “POSITA would have understood that the
’797 Patent’s ‘peripheral bridge’ is ‘a component that interfaces with
peripheral busses or peripheral devices,’” and “POSITA would have
understood that the ‘peripheral bridge’ is not a north bridge, also referred to
as the ‘CPU bridge’ in the ’797 Patent.” Pet. 11–13 (citing Ex. 1001, 24:57–
60, 31:34–32:4, 32:34–58, Figs. 18 and 21).
Patent Owner asserts it “does not believe that any claim terms require
express construction to deny institution,” such that “the claims should be
given their ordinary and customary meaning in light of the specification and
prosecution history, as understood by a person of ordinary skill in the art.”
Prelim. Resp. 5. Patent Owner further “does not believe [‘peripheral
bridge’] requires construction.” Id.
The ’797 patent describes that “[p]eripheral bridge 1846 couples PCI
peripheral bus 1841 with peripheral busses of other formats such as ISA
peripheral bus 1845 and others 1847.” Ex. 1001, 31:38–41; see also id. at
Fig. 21 (Referring to peripheral bridge 1846 as “South Bridge.”). Our
review of the ’797 patent is consistent with Petitioner’s position that the only
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discussions and technical descriptions of “peripheral bridge” does not
include the CPU bridge, i.e., the North Bridge. Moreover, in Figure 21
peripheral bridge 1846 is expressly labeled as “South Bridge,” that is a
device for coupling peripheral devices to other components of the integrated
circuit. See Ex. 1003 ¶ 52 (Dr. Edwards explaining that “the ’797 Patent
identifies only one component as a ‘peripheral bridge,’ and that one
component is peripheral bridge 1846 . . . [t]hat component is labeled as a
‘south bridge.’”).
Although this term is not specifically in dispute and our Decision does
not turn on an express interpretation of this term, to the extent construction
of this term is necessary for understanding the claims and peripheral
component interconnect (PCI) bus transaction technology, based on the
written description of the ’797 patent and the evidence before us we agree
with Petitioner that a person of ordinary skill in the art would have
understood that the “peripheral bridge” is not a north bridge or a “CPU
bridge.”
2. “serial channels” and “serial form”
Independent claims 1, 4, 7, 10, 14, 18, and 21, each require an “LVDS
channel comprising two unidirectional, serial channels” and the step of
“encod[ing] address and data bits . . . in serial form.” See, e.g., Ex. 1001,
37:62–38:3, 38:23–30, 48–55 (emphases added). Independent claims 27, 30,
33, and 36 do not require the step of “encoding address and data bits . . . in
serial form,” but do still recite “two unidirectional serial channels.” See,
e.g., id. at 41:18–38.
Neither Petitioner nor Patent Owner proposes a formal construction
for these terms. See generally, Pet. 10–14; Prelim. Resp. 5. Nevertheless,
Patent Owner posits that “serial” data transmission has a generally accepted
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ordinary meaning. Prelim. Resp. 14–16. According to Patent Owner, the
IEEE Standard Dictionary of Electrical and Electronics Terms, 6th Ed.,
(1996), defines “serial transmission” as “one bit at a time on a single path,”
and “serial interface” as “[a]n interface that transmits data bit by bit rather
than in whole bytes.” Id. (quoting Ex. 2002,9 11).
Consistent with Patent Owner’s interpretation, in its prior art analysis,
Petitioner treats these terms as having ordinary meanings similar to the IEEE
Dictionary, relying on Goodrum’s “serial mode” to meet the “serial
channels” and “in serial form” limitations See, e.g., Pet. 19 (relying on
Goodrum’s “serial mode” for the “serial channels” limitations recited in
claim 1) (citing Ex. 1006, 6:25−31, 106:16−31), 26 (relying on the “serial
mode” in Goodrum to meet “serial channels” limitation recited in claim 4).
Additionally, Patent Owner’s declarant, Marc Levitt, Ph.D., testifies
that the IEEE Dictionary defines “serialization” as “the process of
transmitting coded characters one bit at a time.” Ex. 2001 ¶ 78 (citing Ex.
2002, 11) (emphasis added). Dr. Levitt further testifies that the IEEE
Dictionary indicates that “serial” means the opposite of “parallel”
transmission, which “transmits multiple bits simultaneously.” Id. (citing Ex.
2002, 9 (defining “parallel transmission” as “simultaneous transmission of
all the bits making up a character or byte where each bit travels on a
different path” and contrasting to “serial transmission”), 11 (defining “serial
transmission” and contrasting to “parallel transmission”)).
Patent Owner’s interpretation is also consistent with the Specification
of the ’797 patent. The written descriptions states that “[a] bit based line

9 Our citations to Exhibit 2002 refer to the page number on the bottom, right
corner added by Patent Owner.
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(i.e., a bit line) is a line for transmitting serial bits,” and that “[b]it based
lines typically transmit bit packets and use a serial data packet protocol.”
Ex. 1001, 22:51−52. The written description also explains that “[e]xamples
of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial
Bus (USB) line.” Id. at 22:53−55.
In view of the foregoing, for purposes of this Decision, we adopt
Patent Owner’s interpretation—namely that the ordinary meaning of, “[i]n
data transmission, ‘serial’ is ‘one bit at a time on a single path.’” Prelim.
Resp. 14. And that “serial” means the opposite of “parallel” transmission,
which “transmits multiple bits simultaneously.” Id.; Ex. 2001 ¶ 78; Ex.
2002, 9, 11.
B. Legal Standards of Obviousness
Section 103(a) forbids issuance of a patent when “the differences
between the subject matter sought to be patented and the prior art are such
that the subject matter as a whole would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
(2007).
The question of obviousness is resolved on the basis of underlying
factual determinations, including: (1) the scope and content of the prior art;
(2) any differences between the claimed subject matter and the prior art;
(3) the level of ordinary skill in the art; and (4) when available, evidence
such as commercial success, long-felt but unsolved needs, and failure of
others. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966); see KSR, 550
U.S. at 407 (“While the sequence of these questions might be reordered in
any particular case, the [Graham] factors continue to define the inquiry that
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controls.”). The Court in Graham explained that these factual inquiries
promote “uniformity and definiteness,” for “[w]hat is obvious is not a
question upon which there is likely to be uniformity of thought in every
given factual context.” Graham, 383 U.S. at 18.
The Supreme Court made clear that we apply “an expansive and
flexible approach” to the question of obviousness. KSR, 550 U.S. at 415.
Whether a patent claiming the combination of prior art elements would have
been obvious is determined by whether the improvement is more than the
predictable use of prior art elements according to their established functions.
Id. at 417. To reach this conclusion, however, it is not enough to show
merely that the prior art includes separate references covering each separate
limitation in a challenged claim. Unigene Labs., Inc. v. Apotex, Inc., 655
F.3d 1352, 1360 (Fed. Cir. 2011). Rather, obviousness additionally requires
that a person of ordinary skill at the time of the invention “would have
selected and combined those prior art elements in the normal course of
research and development to yield the claimed invention.” Id.
A claimed invention may be obvious even when the prior art does not
teach each claim limitation, so long as the record contains some reason why
one of skill in the art would modify the prior art to obtain the claimed
invention. See Ormco Corp. v. Align Tech., Inc., 463 F.3d 1299, 1307
(Fed. Cir. 2006). As a factfinder, we also must be aware “of the distortion
caused by hindsight bias and must be cautious of arguments reliant upon ex
post reasoning.” KSR, 550 U.S. at 421. This does not deny us, however,
“recourse to common sense” or to that which the prior art teaches. Id.
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C. Level of Ordinary Skill in the Art
Factors pertinent to a determination of the level of ordinary skill in the
art include: (1) educational level of the inventor; (2) type of problems
encountered in the art: (3) prior art solutions to those problems; (4) rapidity
with which innovations are made; (5) sophistication of the technology, and
(6) educational level of workers active in the field. Envtl. Designs, Ltd. v.
Union Oil Co., 713 F.2d 693, 696–697 (Fed. Cir. 1983) (citing Orthopedic
Equip. Co. v. All Orthopedic Appliances, Inc., 707 F.2d 1376, 1381–82
(Fed. Cir. 1983)). Not all such factors may be present in every case, and one
or more of these or other factors may predominate in a particular case.
Id. Moreover, these factors are not exhaustive but are merely a guide to
determining the level of ordinary skill in the art. Daiichi Sankyo Co. Ltd,
Inc. v. Apotex, Inc., 501 F.3d 1254, 1256 (Fed. Cir. 2007).
In determining a level of ordinary skill, we also may look to the prior
art, which may reflect an appropriate skill level. Okajima v. Bourdeau, 261
F.3d 1350, 1355 (Fed. Cir. 2001). Additionally, the Supreme Court informs
us that “[a] person of ordinary skill is also a person of ordinary creativity,
not an automaton.” KSR, 550 U.S. at 421.
Petitioner asserts that a person of ordinary skill in the art at the time of
the ’797 patent “would have had at least a Master’s Degree in, or a
Bachelor’s Degree in electrical engineering, computer science, or a related
subject and three years of experience working with computer architecture,
computer busses, and related technologies.” Pet. 10 (citing Ex. 1003 ¶ 46).
Patent Owner states that “[f]or the purposes of these preliminary
proceedings, Patent Owner does not dispute the level of skill for a person of
ordinary skill in the art” but “Patent Owner does not waive . . . any argument
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regarding the proper level of skill, and further reserves the right to later
advance additional arguments.” Prelim. Resp. 6.
On this record, Petitioner’s proposed level of ordinary skill in the art
is consistent with our review and understanding of the technology and
descriptions in the ’797 patent and the asserted prior art references. For
purposes of this Decision, we rely on Petitioner’s proposed level of ordinary
skill in the art.
D. Grounds 1 and 2: Claims 4–6, 14–17, 21–23, and 36–38,
Alleged Obviousness over Gulick and Goodrum, and Claims
27–31, 33, and 34, Alleged Obviousness over Gulick, Goodrum,
and McAlear
We address grounds 1 and 2 together because they are both based on
the underlying combination of Gulick and Goodrum. For the reasons
discussed below, on this record, Petitioner has not established a reasonable
likelihood of prevailing on its assertion that at least one of claims 4–6, 14–
17, 21–23, 27–31, 33, 34, and 36–38 would have been obvious.
1. Gulick (Ex. 1004)
Gulick is titled “Non-Addressed Packet Structure Connecting
Dedicated End Points on a Multi-Pipe Computer Interconnect Bus.”
Ex. 1004, code (54). Gulick describes a protocol of a multi-pipe
interconnection bus including sending a non-addressed read or write
transaction request over one of the pipes of a multiple-pipe computer
interconnect bus. Ex. 1004, code (57) (Abstr.). The multiple pipes carry
transactions on a packet multiplexed basis, and a transaction request—sent
over one of the pipes from a source to a target—includes a non-addressed
transaction command. Id. The transaction is performed in a predetermined
location in response to the non-addressed transaction command, and a
transaction response is returned upon completion of the transaction. Id.
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Figure 1 of Gulick is reproduced below.

Gulick’s Figure 1 above, labeled “prior art” illustrates a traditional personal
computer architecture that uses a Peripheral Component Interface (PCI) bus
101 as a connection between a “north bridge” integrated circuit 103 and a
“south bridge” integrated circuit 105. Id. at 1:20–31.
The north bridge in Figure 1 functions generally as a switch
connecting CPU 107, a graphics bus 109, the PCI bus, and a main memory
111. Id. at 1:26–63. The north bridge also contains a memory controller
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function. Id. The south bridge generally provides the interface to the
input/output (I/O) portion of the system. Id. Specifically, the south bridge
105 provides a bridge between the PCI bus and legacy PC-AT (Advanced
Technology) logic, also providing a bridge to a legacy ISA bus 115,
Integrated Device Electronics (IDE) disk interface 117, and Universal Serial
Bus (USB) 119. Id. PCI bus 101 also functions as the major input/output
bus for add-in functions such as network connection 121. Id. Gulick
explains that the PCI bus in the prior art causes a lack of determinism in the
system because any function on the PCI bus can become master of the bus
and tie up the bus, PCI bus load fluctuations can result in uncertain and
irregular quality of service. Id. Therefore, “having a PCI bus as the major
input/output bus means that the major input/output bus of present day
computer systems does not provide proper support for both isochronous and
asynchronous data.” Id.
Figure 3 of Gulick, reproduced below, is an embodiment illustrating a
high level block diagram of a portion of a personal computer system that
utilizes a link 205 to communicate between two integrated circuits 301 and
303, such that “the PCI bus no longer functions as the primary interface
between the processor/memory controller 301 input/output functions,” with
link 205 replacing the PCI bus as the primary interface and also carrying
both isochronous and asynchronous data. Id. at 5:4–20.
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Processor module 301 in Figure 3 includes link interface 305 coupled via
link 205 to link interface 307 in interface module 303. Id. at 5:4–58. Link
205 provides guaranteed bandwidth and latency to each isochronous stream,
while also attempting to minimize latency to asynchronous accesses (such as
CPU-initiated accesses and PCI-initiated accesses). Id.
2. Goodrum (Ex. 1006)
Goodrum is titled “Synchronizing Data between Devices.” Ex. 1006,
code (54). Goodrum discloses a computer system performing data
synchronization using a communication channel, a mass storage device
accessible from the communication channel, and a first device and second
device connected to the communication channel. Id. at 1:5–7, 1:26–37.
Figure 1 of Goodrum as annotated by Patent Owner is reproduced
below.
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Goodrum’s Figure 1 above, illustrates a computer system 10 including
system controller/host bridge circuit 18, i.e., north bridge, and PCI-EISA
bridge 15, i.e., south bridge, connected through primary PCI bus 24 and also
coupled to bridge chip 26a and bridge chip 26b. Id. at 4:65–5:6.
As shown in Figure 1, Bridge chip 26a is coupled to a bridge chip 48a
through a cable 31, and bridge chip 26b is coupled to bridge chip 48b
through a cable 28. Id. at 5:1–22. Bridge chips 48a and 48b provide an
interface with PCI Bus 32a and 32b on two separate expansion boxes 30a
and 30b. Id. at 5:23–29. Expansion boxes 30a and 30b provide plug-in slots
36 for conventional expansion cards (not shown). Id. Goodrum teaches that
cables 28 and 31 can be a High Performance Interface (HIPPI) cable for
carrying differential signals via “IEEE Draft Standard for Low-Voltage
Differential Signals (LVDS).” Id. at 57:30–46.
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3. McAlear (Ex. 1007)
McAlear is titled “Local Area Network Incorporating Universal Serial
Bus Protocol.” Ex. 1007, code (54). McAlear discloses “local area
networks . . . comprising a LAN hub, a plurality of outer hub devices
connected to the LAN hub via a respective plurality of LAN links and a
plurality of USB devices and/or LAN computers connected to the plurality
of outer hub devices via a respective plurality of USB links.” Id., code (57)
(Abstr.). The outer end hubs communicate with the USB devices and LAN
computers using a USB protocol having time sensitive aspects, and the outer
end hubs further communicate with the LAN hub using a LAN protocol that
permits the outer hub device to be further than 5 meters from the LAN hub.
Id. In one embodiment, McAlear describes a LAN computer that
communicates with a USB device by addressing a LAN hub in the IP (or
Ethernet) protocol, and encapsulating the USB protocol within the IP (or
Ethernet) protocol. Id. at 40:35–42.
4. Independent Claims 4, 14, 21, 27, 30, 33, and 36
Each of independent claims 4, 14, 21, 27, 30, 33, and 36 include the
same or similar limitation to that of claim 4[c], namely the step of
“connecting a Low Voltage Differential Signal (LVDS) channel directly to
the CPU on the printed circuit board, the LVDS channel comprising two
unidirectional, serial channels that transmit data in opposite directions.”
See, e.g., Ex. 1001, 38:21–24 (emphasis added). Independent claims 4, 14,
and 21 include the same or similar additional limitation as claim 4[e],
reciting the step of “conveying encoded address and data bits of a Peripheral
Component Interconnect (PCI) bus transaction in serial form over the serial
channels.” Id. at 38:28–30 (emphasis added).

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a) Petitioner’s Arguments
Petitioner relies on Gulick for initial limitations 4[a] and 4[b],
specifically that Gulick teaches a computer system including “link 205” for
improved isochronous and asynchronous communications between
processor module 301 and interface module 303 “formed on printed circuit
boards (PCBs).” Pet. 20–21 (citing Ex. 1003 ¶¶ 68–69; Ex. 1004, 5:4–7,
10–14). Petitioner also relies on Gulick and the testimony of Dr. Edwards
for limitation 4[g], arguing that a person of ordinary skill in the art would
have understood that “applying power to the computer system is an obvious
step.” Id. at 31 (citing Ex. 1003 ¶ 78).
Petitioner turns to Goodrum for the steps of limitations 4[c]–[f] which
flow from claimed step 4[c], “connecting a Low Voltage Differential Signal
(LVDS) channel directly to the CPU on the printed circuit board, the LVDS
channel comprising two unidirectional, serial channels.” Ex. 1001, 38:21–
23. Petitioner argues that Goodrum discloses differential signaling to
improve communication between cable interfaces of a PCI-to-PCI bridge
and, that “Goodrum explicitly discloses using LVDS signaling over the
cable . . . and operating in a serial mode.” Pet. 26 (citing Ex. 1006, 57:30–
49, 106:16–31, 6:25–31).
b) Patent Owner’s Arguments
Patent Owner argues that Petitioner has failed to meet its burden as to
the challenged claims for at least two reasons, first because neither Gulick
nor Goodrum discloses the LVDS channel comprising “serial channels” as
recited in each of the independent claims. Prelim. Resp. 8, 14–18. Second,
because Petitioner has failed to provide adequate reasoning supported by
evidentiary underpinnings sufficient to support a motivation to combine
Gulick and Goodrum. Id. at 8, 28–38. The combination of Gulick and
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Goodrum fails, Patent Owner argues, because: (i) the Petition’s reasons to
combine depend on generalized goals that Gulick does not actually teach;
(ii) the Petition does not address Gulick’s actual goal of determinism or how
and why a POSITA would use Goodrum to address that goal; and (iii) the
Petition does not address that Goodrum would defeat Gulick’s goal of
reducing pins. Id. at 31–38.
c) Analysis
By way of example, we focus our analysis initially on independent
claim 4 as it contains both “serial channels” and “in serial form” limitations.
Claim step 4[c] requires “connecting a Low Voltage Differential Signal
(LVDS) channel directly to the CPU on the printed circuit board, the LVDS
channel comprising two unidirectional, serial channels that transmit data in
opposite directions.” Ex. 1001, 38:21–24. Claim step 4[e] also recites the
step of “conveying encoded address and data bits of a Peripheral Component
Interconnect (PCI) bus transaction in serial form over the serial channels.”
Id. at 38:28–30.
Acknowledging that “Gulick does not disclose the link 205 as
comprising a first LVDS channel or a first LVDS,” Petitioner turns to
Goodrum’s disclosure of differential signaling over LVDS cable for
conveying PCI bus transactions to meet element 4[b]. Pet. 25 (citing Ex.
1006, 4:65–5:6, 5:44–51, 6:25–27, 57:30–49). With respect to the claimed
“serial channels” and conveying bits in “serial form,” Petitioner asserts that
Goodrum discloses “operating in a serial mode.” Pet. 26 (citing Ex. 1006,
106:16–31, 6:25–31).
Petitioner argues that a person of ordinary skill in the art would have
been motivated to improve Gulick’s link interfaces by substituting
Goodrum’s LVDS cable for several reasons, “less expensive, better noise
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immunity, minimized EM radiation etc.” Pet. 19 (citing Ex. 1006, 57:30–
44). Considering Gulick’s Figure 3, Petitioner argues that a person of skill
in the art would have modified Gulick’s link interface 305, link 205, link
interface 307 “to incorporate Goodrum’s cable interface, cable and LVDS
signaling of PCI bus transactions for at least the reasons set forth above.”
Id. at 26 (citing Ex. 1003 ¶ 73).
In its Preliminary Response, Patent Owner counters that the
combination of Gulick and Goodrum does not disclose “serial transmission
of address and data bits,” or transmitting address bits, data bits, and byte
enable information bits of a PCI bus transaction “in serial form.” Prelim.
Resp. 15. Patent Owner points out that “[t]he Petition does not assert that
Gulick discloses transmitting PCI bits in serial form.” Id. (citing Pet.
22−26). Patent Owner contends that Goodrum does not disclose “serial
transmission of address bits, data bits, and/or byte enable information bits.”
Id. at 18. For the reasons explained below, we agree with Patent Owner that
the combination of Gulick and Goodrum, and specifically Goodrum, does
not teach or suggest the “serial channels” and “in serial form” limitations.
For one thing, we note that the portions of Goodrum cited by
Petitioner for teaching “a serial mode” in fact disclose transmitting
“interrupts,” not transmitting encoded address and data bits of a PCI bus
transaction as required by certain of the challenged claims. Pet. 19, 26
(citing Ex. 1006, 6:25−31 (describing “a serial stream” for interrupts),
106:16−31 (describing “serial mode” for “interrupt request signals” on
“interrupt request lines”)).
Indeed, Goodrum discloses differential signaling in parallel over a
“cable designed to support the High Performance Parallel Interface (HIPPI)
standard” and “the HIPPI cable specifications,” not “serial channels” or “in
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serial form” as required by the challenged claims at issue. Ex. 1006,
57:22−49, 58:8−14, Fig. 16 (emphasis added). Tellingly, the portions of
Goodrum cited by Petitioner to teach “conveying PCI transactions using
differential signaling over a cable (e.g., cable 28)” and “[t]wenty wire pairs
of the cable 28 are used for downstream communication and 20 more for
upstream communication,” in fact, disclose parallel transmissions, not serial
transmissions. Pet. 19, 25−26, 59 (citing Ex. 1006, 57:30−49, 58:8−9).
Goodrum is clear that cable 28 is a “50-pair HIPPI cable” (a parallel cable).
Ex. 1006, 57:22−24 (“a cylindrical 50-pair shielded cable designed to
support the High Performance Parallel Interface (HIPPI) standard”), 58:10
(“the 50-pair HIPPI cable 28”).
In support of Patent Owner’s arguments, Dr. Levitt persuasively
testifies that “Goodrum’s data transfers are done as parallel transmissions,
sending a 60-bit message over the parallel cable in three time-multiplexed
phases of 20 parallel bits each.” Ex. 2001 ¶ 81 (citing Ex. 1006, 52:22−45,
55:14−56:3, Figs. 14, 15A). Dr. Levitt testifies further that “Goodrum
promotes the benefits of its parallel cable interface over ‘serial methods’
such as fiber optics,” to transmit address and data bits. Id. (citing Ex. 1006,
57:36−39 (“less expensive than fiber optics for this short distance and less
complex to interface than other serial methods”)). Moreover, Petitioner’s
reason to combine Goodrum with Gulick relies on those advantages
disclosed in Goodrum that are for transmitting data in parallel over a HIPPI
cable, not for transmitting on “serial channels” as required by the challenged
claims. Pet. 19, 26 (citing Ex. 1006, 57:30−44).
We credit Dr. Levitt’s testimony because it is consistent with
Goodrum’s disclosure and the general knowledge of an ordinarily skilled
artisan. See, e.g., Ex. 1006, 57:22−49, 55:14−56:3, 58:8−14, Figs. 14, 15A
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16; Ex. 2002, 9 (defining “parallel transmission” as “[s]imultaneous
transmission of all the bits making up a character or byte where each bit
travels on a different path” and contrasting to “serial transmission”), 11
(defining “serial transmission” as “one bit at a time on a single path,” and
“serial interface” as “[a]n interface that transmits data bit by bit rather than
in whole bytes”).
Significantly, even if a person of ordinary skill in the art understood
that Gulick’s link interfaces “could have been modified to incorporate
Goodrum’s cable interface” as Dr. Edwards testifies, neither Petitioner nor
Dr. Edwards explains why one of ordinary skill in the art would have
modified Goodrum’s “true differential” signaling that transmits data in
parallel over a HIPPI cable to use “serial channels,” or additionally,
accomplish the step of “conveying encoded address and data bits of a
Peripheral Component Interconnect (PCI) bus transaction in serial form over
the serial channels” as is further required by certain challenged claims. Ex.
1003 ¶ 73; Ex. 1001, 38:28–30; Pet. 16−20, 22−30; Ex. 1003 ¶¶ 70−75.
In light of the foregoing, we determine that Petitioner fails to show
that the combination of Gulick and Goodrum discloses “serial channels” as
required by each of independent claims 4, 14, 21, 27, 33, and 36, and further
fails to teach conveying data addresses and bits “in serial form” as required
by independent claims 4, 14, and 21. Additionally, as to independent claims
27, 33, and 36, Petitioner’s combination of Gulick, Goodrum, and McAlear
do not cure this deficiency.
5. Dependent Claims 5–6, 15–17, 22–23, 37–38, 28–31,
and 34
Dependent claims 5–6, 15–17, 22–23, 37–38, 28–31, and 34 depend
directly or indirectly from the independent claims 4, 14, 21, 27, 33, and 36,
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and by virtue of their dependency include all the limitations of the respective
independent base claim and, therefore, do not cure the deficiency in the
underlying combination of Gulick and Goodrum. Thus, we determine
Petitioner has not demonstrated a reasonable likelihood of prevailing on
either challenge.
E. Grounds 3 and 4: Claims 7–9 and 18–20, Alleged Obviousness
over Hart and Goodrum, and Claims 1–3 and 10–13 Alleged
Obviousness over Hart, Goodrum, and McAlear
On this record, Petitioner has not established a reasonable likelihood
of prevailing on its assertion that at least one of claims 1–3, 7–9, 10–13, and
18–20 would have been obvious for the reasons explained below.
1. Hart (Ex. 1008)
Hart is titled “Method and Apparatus for Providing a Processor
Module for a Computer System.” Ex. 1008, code (54). Hart discloses a
circuit board including an interface for coupling the circuit board to a
peripheral subsystem via a socket, a processor that receives signals of a first
voltage level, a first signal line, and a second signal line, with the first signal
line coupled to the interface and providing a reference signal to the
peripheral subsystem that indicates the first voltage level, and the second
signal line also coupled to the interface and providing a subsystem signal
back from the peripheral subsystem after the signal has been converted to
the first voltage level. Id., code (57) (Abstr.).
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Figure 2 of Hart is reproduced below.

Figure 2, above, illustrates a computer system in which an electronic
component (processor module 220) includes a circuit board containing
processor 200, voltage regulator 201, primary bridge A 203, clock 202, and
associated signal lines and interfaces. Id. at 3:36–42.
Processor module 220 in Figure 2 includes an interface inserted into a
system socket 223, thereby coupling the signal lines of the circuit board of
processor module 220 to corresponding signal lines of a peripheral
subsystem having separate circuit boards that contain system memory 204,
bus agents 1–4, secondary bridge B 205, and voltage conversion circuit 221.
Id. at 3:41–4:13. Processor 200 is coupled to primary bridge 203 by way of
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host bus 208. Id. Voltages regulator 201 is coupled to and provides a
voltage supply to processor 200, and clock 202 is coupled to and provides a
clock signal to processor 200 and to bridge 203. Id. Primary bridge 203 is
also coupled to two other buses, peripheral component interconnect (PCI)
bus 206 and memory bus 209. Id. The signal lines that make up PCI bus
206 couple primary bridge 203, through system socket interface 223, to PCI
bus agents 1 and 2 as well as to secondary bridge 205. Id. Memory bus 209
couples bridge 203, through system socket interface 223, to system main
memory 204. Id. Clock 202 includes a clock signal output that provides a
PCI clock signal to PCI bus agents along the PCI clock signal line that
extends from clock 202, across the system socket interface 223, to the
peripheral subsystem side comprising the circuit boards containing PCI bus
agents 1 and 2. Id. Secondary bus bridge 205 is coupled to bus agents 3 and
4 by way of secondary bus 207. Id. Bridge 205 is also coupled to processor
200, through interface 223, by subsystem signal line 210. Id. The system in
Figure 2 may be implemented in a mobile computer system, or in a desktop
computer system or server. Id. at 4:14–19.
2. Independent Claims 1, 7, 10, and 18
Similar to claims 4, 14, and 21 discussed above, each of independent
claims 1, 7, 10, and 18 include the limitations of “the LVDS channel
comprising two unidirectional, serial channels,” and “conveying encoded
address and data bits of a Peripheral Component Interconnect (PCI) bus
transaction in serial form over the serial channels.” See, e.g., Ex. 1001,
37:62–63, 38:1–4.
In the same manner as the first two challenges, Petitioner
acknowledges that “Hart does not disclose the primary bridge 203 or socket
interface 223 as comprising an LVDS channel comprising two
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unidirectional, serial channels.” Pet. 74. Also, as in the first two challenges,
Petitioner turns to Goodrum to supply the missing limitation of the LVDS
channel arguing that “Goodrum explicitly discloses using LVDS signaling
over the cable . . . and operating in a serial mode.” Id. (citing Ex. 1006,
6:25–31, 57:45–49, 106:16–31). For the same reasons as explained above
with respect to the combination of Gulick and Goodrum, we determine also
for the combination of Hart and Goodrum, that Goodrum fails to disclose
both the “serial channels” and “in serial form” limitations recited in claims
1, 7, 10, and 18. See Section II.D.4.
Accordingly, Petitioner has failed to show that the combination of
Hart and Goodrum discloses “serial channels” and conveying data addresses
and bits “in serial form” as required by independent claims 1, 7, 10, and 18.
Additionally, as to independent claims 1 and 10, Petitioner’s contentions as
to the combination of Hart, Goodrum, and McAlear do not cure this
deficiency.
3. Dependent Claims 2–3, 8–9, 11–13, and 19–20
Dependent claims 2–3, 8–9, 11–13, and 19–20 depend directly or
indirectly from the independent claims 1, 7, 10, and 18, and therefore do not
cure the deficiency in the underlying combination of Hart and Goodrum, and
so we determine Petitioner has not demonstrated a reasonable likelihood of
prevailing on these challenges.
F. Ground 5: Claims 32 and 35, Alleged Obviousness over Gulick,
Goodrum, McAlear, and Sauber
Claim 32 depends directly from independent claim 30, and claim 35
depends from claim 34 which in turn depends from independent claim 33.
Ex. 1001, 42:1–4, 20–23. Both dependent claims recite the additional
limiting step of “conveying Transition Minimized Differential Signaling
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(TDMS) signals over the second differential signal channel.” Id. Petitioner
relies on Sauber for teaching sending TDMS signals over the second LVDS
channel. Pet. 89–91. Sauber, however, does not cure the deficiency in the
underlying combination of Gulick and Goodrum. Thus, on the current
record, Petitioner has not made a sufficient showing that the combination of
Gulick, Goodrum, McAlear, and Sauber teaches the subject matter of claims
32 and 35 and so we determine Petitioner has not demonstrated a reasonable
likelihood of prevailing on this challenge.
III. CONCLUSION
For the reasons discussed above, we determine that Petitioner has not
demonstrated a reasonable likelihood of showing that at least one of claims
1–23 and 27–38 of the ’797 patent is unpatentable. Therefore, we decline to
institute a trial on all challenged claims and all asserted grounds of
unpatentability. See SAS Inst., Inc. v. Iancu, 138 S. Ct. 1348, 1355–56
(2018).
IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that the Petition is denied, and no trial is instituted.

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FOR PETITIONER:
Gianni Minutolli
Harpreet Singh
Alan Limbach
DLA PIPER LLP (US)
gianni.minutoli@dlapiper.com
harpreet.singh@dlapiper.com
alan.limbach@dlapiper.com

FOR PATENT OWNER:
Cyrus Morton
Derrick Carman
ROBINS KAPLAN LLP
cmorton@robinskaplan.com
dcarman@robinskaplan.com