8176445 et al.

Patent Trials and Appeals Board

Nov 2, 2021

2021004829 (P.T.A.B. Nov. 2, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
96/000,290 06/25/2019 8176445 50357.2 8324
167839 7590 11/02/2021
King & Wood Mallesons LLP
500 Fifth Avenue
50th Floor
New York, NY 10110
EXAMINER
MENEFEE, JAMES A
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/02/2021 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte IYM TECHNOLOGIES LLC
Patent Owner and Appellant
____________

Appeal 2021-004829
Reexamination Control 96/000,290
Patent 8,176,445 B1
Technology Center 3900
____________

Before JOHN A. JEFFERY, ERIC B. CHEN, and MICHAEL R. ZECHER,
Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL
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Pursuant to 35 U.S.C. §§ 134(b) and 306, Patent Owner1 appeals from
the final rejection of claims 1, 2, 4–7, 9–12, and 14. Claims 3, 8, 13, and
15–20 have been cancelled. (Final Act. 4.)
A telephonic oral hearing was held on September 22, 2021. The
record includes a written transcript of the oral hearing, mailed October 12,
2021. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

STATEMENT OF THE CASE
Reexamination Proceedings
A request for supplemental examination of U.S. Patent No. 8,176,445
B1 (“the ’445 patent”) was filed on June 25, 2019 and assigned Control No.
96/000,290. On October 8, 2019, ex parte reexamination was ordered under
35 U.S.C. § 257 in connection with the supplemental examination. The ’445
patent, entitled “Method and System for Optimizing Integrated Circuit
Layout,” issued May 8, 2012 to Qi-De Qian, based on U.S. Patent
Application No. 12/181,460, filed July 29, 2008. The ’445 patent is said to
be a continuation-in-part of U.S. Patent Application No. 10/907,814,
April 15, 2005, now U.S. Patent No. 7,448,012 (“the ’012 patent”), issued
November 4, 2008.

1 Patent Owner identifies the real party in interest as IYM Technologies
LLC. (Appeal Br. 5.) Patent Owner also states that “General Patent
Corporation is the Managing Member of and owns a 50% membership
interest in IYM Technologies LLC.” (Id.)
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Claimed Subject Matter
The claims are directed to optimizing integrated circuit layouts,
including analyzing a constraint relationship among objects in an initial
layout, constructing local modifications to the constraint relationship,
forming new constraint relationships by combining initial constraint
relationships with their local modifications, and producing a new layout by
implementing the new constraint relationships. (Abstract.)

Related Litigation
The ’012 patent, the parent application of the’445 patent, was subject
to the following petitions for inter partes reviews: (i) IYM Techs. LLC v.
RPX Corp., IPR2017-01886 (PTAB Mar. 6, 2019) aff’d, 796 F. App’x 752
(Fed. Cir. 2020); and (ii) IYM Techs. LLC v. RPX Corp., IPR2017-01888
(PTAB Mar. 6, 2019) dismissed, 798 F. App’x 642 (Fed. Cir. 2020).

The Claims
Claim 1 is illustrative of the claimed subject matter, and is reproduced
below with disputed limitations in italics:
1. A method suitable for integrated circuit layout
processing using one or more microprocessors, the method
comprising the steps of:
providing an initial design layout;
building constraint relationships associated with said
initial design layout;
formulating at least one location dependent modification
to said constraint relationships;
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combining said location dependent modifications with
said constraint relationships to form location dependent
constraint relationships; and
implementing said location dependent constraint
relationships, using said microprocessors, in a manner that is
substantially in compliance with design rules;
whereby producing a new design layout with specific
improvements that are derived from local layout conditions

REFERENCES
Name Reference Date
Bamji et al. US 5,663,891 Sept. 2, 1997
Balasinski et al. US 6,681,376 B1 Jan. 20, 2004
Côté US 6,745,372 B2 June 1, 2004
Kroyan et al. US 7,523,429 B2 Apr. 21, 2009
Lukanc et al. US 7,313,769 B1 Dec. 25, 2007
Gerard A. Allan et al., An Yield Improvement Technique for IC Layout
Using Local Design Rules, 11 IEEE Transactions on Computer-Aided
Design 1355–62 (1992).

A. Claims 1, 9, and 11 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Allan.
B. Claims 2, 4, 10, and 12 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Allan and Lukanc.
C. Claim 5 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Allan and Bamji.
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D. Claims 6, 7, and 14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Allan and Balasinski.2
E. Claims 1 and 9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Côté.
F. Claims 2, 4, 10, and 12 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Côté and Lukanc.
G. Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Côté and Kroyan.
H. Claim 5 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Côté and Bamji.
I. Claims 6, 7, and 14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Côté and Balasinski.3
Patent Owner relied upon the following to rebut the Examiner’s
obviousness rejections:
Declaration under 37 C.F.R. § 1.132 of Puneet Gupta, Ph.D., dated
June 21, 2020 (“Gupta Declaration”).

2 Patent Owner does not present any arguments with respect to the rejection
of dependent claims 2, 4–7, 10, 12, and 14 under 35 U.S.C. § 103(a) over
various combinations of Allan, Lukanc, Bamji, and Balasinski. (Appeal
Br. 28.) Thus, any such arguments are deemed to be waived.
3 Patent Owner does not present any arguments with respect to the rejection
of dependent claims 2, 4–7, 10–12, and 14 under 35 U.S.C. § 103(a) over
various combinations of Côté, Lukanc, Kroyan, Bamji, and Balasinski.
(Appeal Br. 45.) Thus, any such arguments are deemed to be waived.
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OPINION
§ 103(a) Rejection—Allan
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 18–20;
see also Reply Br. 5) that Allan does not teach the limitation “building
constraint relationships associated with said initial design layout,” as recited
in independent claim 1.
The Examiner found that the global design rules (GDR) of Allen,
which bind the layout of integrated circuits, correspond to the limitation
“building constraint relationships associated with said initial design layout.”
(Final Act. 19; see also Ans. 4.) We agree with the Examiner’s findings.
Independent claim 1 recites “building constraint relationships
associated with said initial design layout.” (Col. 17, ll. 42–43 (emphasis
added).) With respect to the term “constraint relationships,” the ’445 patent
discloses the following:
In a layout, the constraint relationships define the
minimal requirement for a layout to be manufacturable and
functional. They require the coordinate variables of the layout
object to satisfy expressions in the form of Ci( . . . xi,yi,xj,yj . . .
xm,ym)>Dij, where Ci is a function of the coordinate variables
of layout objects xi,yi, xj,yj, and xm,ym; Dij is a constant; and
I,j,m are integer numbers.
(Col. 9, ll. 16–22 (emphasis added).)
In the simple one dimensional case, a typical constraint
relationship is expressed in the form xi-xj>dij_old, where xi
and xj are locations of two interacting polygon edges in the
layout, and dij_old is the constraint distance between these two
edges, which can come form of factory issues design rule or
from the intent of the designer.
(Col. 9, ll. 28–33 (emphasis added).)
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As discussed earlier, a constraint relationship is an
equation or inequality among coordinate variables of the layout
objects in the form of Ci( . . . xi,yi,xj,yj . . . xm,ym)>Dij, such
as xi-xj>dij_old.
(Col. 9, l. 65 to col. 10, l. 2 (emphasis added).)
Thus, under the broadest reasonable interpretation consistent with the
Specification of the ’445 patent, we interpret “constraint relationships” as
applying the minimal requirement for a layout to be manufacturable and
functional, for example, the inequality xi-xj>dij_old.
Allen relates to “local design rules” for the layout of integrated
circuits (IC), also described as “IC layout rules that define the optimum
feature size and spacing in relation to the surrounding geometry and are used
to increase the yield of IC’s.” (Abstract.) Allen initially explains that “the
design rules are applied over the whole of the layout area and will, therefore,
be referred to as global design rules (GDR)” and “global rules determine
minimum size and spacing and hold over the whole design, but these rules
should not be used to determine the maximum feature size of circuit.”
(P. 1355 (I).) Because Allan explains that GDR’s determine minimum size
and spacing over the whole design, Allan teaches the limitation “building
constraint relationships associated with said initial design layout.”
Patent Owner argues the following:
For example, if a constraint relationship is “space>= 100
nm,” that means that the space between two layout objects must
be limited or constrained to be at least 100 nm. If the space is
less than 100 nm, the constraint is not met. The dispute turns
on whether the recited “constraint relationships” limit the scope
of the claimed invention. The Examiner appears to believe that
a mathematical expression in the form of an inequality can be a
“constraint relationship” regardless of whether the layout
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satisfies such inequality. Patent Owner submits that the recited
“constraint relationships” are material limitations on the scope
of the claims, and thus serve as limits on where objects can be
placed in a layout.
(Appeal Br. 18 (citations omitted); see also Reply Br. 5.) In particular,
Patent Owner argues that “[t]he specification teaches that there is a direct
correspondence between the ‘constraint relationships’ and the layout
geometry” and accordingly, “‘constraint relationships’ are not merely any
inequality that may or may not be met, but limits that the layout should
satisfy.” (Appeal Br. 20.) However, Patent Owner’s arguments are contrary
to the broadest reasonable interpretation of “constraint relationships”
consistent with the Specification. As discussed previously, we interpret
“constraint relationships” as applying the minimal requirement for a layout
to be manufacturable and functional, for example, an inequality.
Thus, we agree with the Examiner that Allan would have rendered
obvious the subject matter of independent claim 1, which includes the
limitation “building constraint relationships associated with said initial
design layout.”
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 21;
see also Reply Br. 4–6) that Allan does not teach the limitation “combining
said location dependent modifications with said constraint relationships to
form location dependent constraint relationships,” as recited in independent
claim 1.
The Examiner found that the local design rules (LDR) of Allen, which
determine changes to the layout generated by the GDR, correspond to the
limitation “formulating at least one location dependent modification to said
constraint relationships.” (Final Act. 19.) The Examiner further found that
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Figure 2 of Allan, which illustrates an algorithm for determining a new
width of a metal track, including the expressions “Space Above Segment >=
LDR + GDR” and “Space Below Segment >= LDR + GDR,” corresponds to
the limitation “combining said location dependent modifications with said
constraint relationships to form location dependent constraint relationships.”
(Final Act. 19–20; see also Ans. 4–5.) We agree with the Examiner’s
findings.
As discussed previously, Allen explains that “the design rules are
applied over the whole of the layout area and will, therefore, be referred to
as global design rules (GDR)” and “global rules determine minimum size
and spacing and hold over the whole design, but these rules should not be
used to determine the maximum feature size of circuit.” (P. 1355 (I).)
Moreover, Allen explains that “[l]ocal design rules [LDR’s] are used to
determine where changes in layout generated from GDR sets should be
performed” and “[t]he purpose of LDR’s is to define maximum feature sizes
in relation to the available space around the geometry under consideration.”
(P. 1355 (II).) Figures 1(a)–1(d) of Allan, reproduced below, illustrates the
application of LDR’s to increase a track width.
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FIG. 1
In particular, Figure 1(a) illustrates the original layout, with an LDR applied
to the bottom track. (P. 1357 (IV)(A)(1).) Moreover, as illustrated in
Figures 1(b)–1(d), “[i]f there is space above or below the segment greater
than that required for the GDR and the LDR separation, a new wider
segment is generated” and “if there are no violations the change in width is
accepted,” such that “[t]he resulting segments are then merged.” (Id.)
Figure 2 of Allan, reproduced below, illustrates the algorithm to
determine “[i]f there is space above or below the segment greater than that
required for the GDR and the LDR separation” in order to generate the new
wider metal track segment, which include the following instructions: (i)
“Space Above Segment >= LDR + GDR” and (ii) “Space Below Segment >=
LDR + GDR.” (P. 1357 (IV)(A)(2), Fig. 2.)
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FIG. 2
Because the algorithm of Allan for generating the wider track segment
includes both LDR’s and GDR’s, Allan teaches the limitation “combining
said location dependent modifications with said constraint relationships to
form location dependent constraint relationships.”
Patent Owner argues the following:
However, “Space [Above/Below] Segment>= LDR + GDR” is
not a “constraint relationship” on the layout. If it were, Allan’s
method would take some action to limit the geometry of the
layout so that the space above or below a segment is at least as
great as “LDR + GDR”; however, Allan does not do so. There
is no dispute that if the space above or below a segment is less
than “LDR + GDR,” Allan takes no action to increase the
spacing to make it greater than or equal to “LDR + GDR”;
Allan does nothing.
(Appeal Br. 21 (emphasis omitted); see also Reply Br. 4–6.) Again, Patent
Owner’s arguments are contrary with the broadest reasonable interpretation
of “constraint relationships” consistent with the Specification. As discussed
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previously, we interpret “constraint relationships” as applying the minimal
requirement for a layout to be manufacturable and functional, for example,
an inequality. Moreover, Patent Owner’s arguments are not commensurate
in scope with independent claim 1, because the claim does not require
always taking action to limit the geometry of the layout.
Thus, we agree with the Examiner that Allan would have rendered
obvious the subject matter of independent claim 1, which includes the
limitation “combining said location dependent modifications with said
constraint relationships to form location dependent constraint relationships.”
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 22–25;
see also Reply Br. 6–8) that Allan does not teach the limitation
“implementing said location dependent constraint relationships,” as recited
in independent claim 1.
The Examiner found that Figure 2 of Allan, which illustrates an
algorithm for determining the new width of a metal track based upon LDR’s
and GDR’s, and the “LocDes” program of Allen, which checks design rules,
collectively correspond to the limitation “implementing said location
dependent constraint relationships.” (Final Act. 20; see also Ans. 4–5.) We
agree with the Examiner’s findings.
Independent claim 1 recites “implementing said location dependent
constraint relationships.” (Col. 17, ll. 49–50 (emphasis added).) With
respect to the term “implementing,” the ’445 patent discloses the following:
In another preferred embodiment, the local constraints
are implemented one at a time using heuristic search
procedures. This procedure searches the neighborhood of a
given edge for spaces that can be used to satisfy the new
constraint distance dij_new. When dij_new is equal or smaller
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than dij_old, the constraint relationship form xj-xi>dij_old
(>dij_new) is always satisfied and no edge movement is
mandatory. If, on the other hand, the new constraint distance is
larger than the initial constraint distance, edge movement
becomes mandatory and extra space must be found to move the
edge in order to satisfy the new constraint distance.
(Col. 16, ll. 18–28 (emphasis added).)
Thus, under the broadest reasonable interpretation consistent with the
Specification of the ’445 patent, we interpret “implementing” as determining
if an equation (or inequality) relating to a distance layout objects has been
satisfied (e.g., xj-xi>dij_old>dij_new), in which movement of layout objects
is mandated only if the equation (or inequality) is violated.
As discussed previously, Figure 2 of Allan illustrates the algorithm to
determine “[i]f there is space above or below the segment greater than that
required for the GDR and the LDR separation” in order to generate a new
wider metal track segment, which include the following instructions: (i)
“Space Above Segment >= LDR + GDR” and (ii) “Space Below Segment >=
LDR + GDR.” (P. 1357, Fig. 2.) Moreover, Allan explains that the
“LocDes” program is “a design rule checker that attempts small changes in
layout based on the LDR’s, accepting only those changes that do not violate
any of the global or other local design rules.” (P. 1356 (IV).) Because Allan
explains that both the “LocDes” program of Allan and the algorithm
illustrated in Figure 2 of Allen check for compliance with both LDR’s and
GDR’s, Allan teaches the limitation “implementing said location dependent
constraint relationships.”
Patent Owner argues “that ‘implementing’ constraint relationships
means finding adjustments to the positions of the layout objects in the
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original layout that cause the positioning of the layout objects to comply
with the constraint relationships” (Appeal Br. 22) and “taking action after
confirming that a mathematical relation is not violated is not ‘implementing’
a ‘constraint relationship’” (id. at 25 (emphasis omitted)). In particular,
Patent Owner argues that “Allan may involve the relations ‘Space
[Above/Below] Segment>= LDR + GDR’ as part of a different operation, it
does not implement them as constraint relationships as the claims require,”
because “if the space between tracks is smaller than ‘LDR + GDR,’ Allan
does not increase the space to make it at least as wide as ‘LDR + GDR.’”
(Id. (emphasis omitted); see also Reply Br. 6–8.) However, Patent Owner’s
arguments are contrary to the broadest reasonable interpretation of
“implementing” consistent with the Specification. As discussed previously,
we interpret “implementing” as determining if an inequality relating to a
distance layout objects has been satisfied, in which movement of layout
objects is mandated only if the inequality is violated.
Thus, we agree with the Examiner that Allan would have rendered
obvious the subject matter of independent claim 1, which includes the
limitation “implementing said location dependent constraint relationships.”
Accordingly, we sustain the Examiner’s rejection of independent
claim 1 under 35 U.S.C. § 103(a).
Independent claim 9 recites limitations similar to those discussed with
respect to independent claim 1, and Patent Owner has not presented any
additional substantive arguments with respect to this claim. We sustain the
Examiner’s rejection of independent claim 9, as well as dependent claim 11
for the same reasons discussed with respect to independent claim 1.
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§ 103(a) Rejection—Côté
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 34–
43) that Côté does not teach the limitations “building constraint relationships
associated with said initial design layout,” “formulating at least one location
dependent modification to said constraint relationships,” and “combining
said location dependent modifications with said constraint relationships to
form location dependent constraint relationships,” as recited in independent
claim 1.
The Examiner found that design rules 505 of Côté, associated with
original layout 510, correspond to the limitation “building constraint
relationships associated with said initial design layout” (Final Act. 29; see
also Ans. 8) and found that local layout requirements 518 of Côté
correspond to the limitation “formulating at least one location dependent
modification to said constraint relationships” (Final Act. 30; see also
Ans. 8–9). The Examiner further found that layout optimizer 520 of Côté
and the new target layout T’, as illustrated in Figure 6, collectively
correspond to the limitation “combining said location dependent
modifications with said constraint relationships to form location dependent
constraint relationships.” (Final Act. 30; see also Ans. 9–10.) We agree
with the Examiner’s findings.
Côté relates to “simulating effects of a manufacturing process on an
integrated circuit to enhance process latitude and/or reduce layout size.”
(Col. 1, ll. 10–13.) In the “Background” section, Côté explains that “[a]
layout of an integrated circuit is typically created in accordance with a set of
design rules that specify a number of constraints, such as minimum spacings
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or minimum line widths, to increase the likelihood that the finished
integrated circuit functions properly in spite of different manufacturing
effects.” (Col. 1, ll. 58–63.) Moreover, Côté explains that “the use of
design rules can lead to sub-optimal layouts” (col. 2, ll. 5–6) and “[i]t may
be preferable to use a larger spacing between shapes whenever possible to
improve ‘process latitude’” (col. 2, ll. 10–12).
Figure 5 of Côté, which is a flow chart illustrating the generation of a
layout, including layout creation process 503, design rules 505, simulated
printed image 514, image analyzer 516, local layout requirements 518, and
layout optimizer 520, is reproduced below.
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In reference to Figure 5, Côté explains that “[l]ayout creation process 503
takes as input a design 502 and ensures that the resulting layout 510 satisfies
a set of design rules 505” (col. 5, ll. 12–15), and “image analyzer 516 uses
the simulated printed image 514 to generate local layout requirements 518 to
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optimize the process latitude and/or layout characteristics, e.g. area,” which
“feed into a layout optimizer 520” (col. 5, ll. 30–34). Côté further explains
that “layout optimizer 520 attempts to update the layout to produce a
layout 522 with enhanced process latitude.” (Col. 5, ll. 37–39.) Because
Côté explains that layout creation process 503 satisfies design rules 505,
Côté teaches the limitation “building constraint relationships associated with
said initial design layout.” Moreover, because Côté explains that local
layout requirements 518 are generated to optimize the process latitude or
layout characteristics, Côté teaches the limitation “formulating at least one
location dependent modification to said constraint relationships.”
Figure 6 of Côté, partially reproduced below, illustrates a process-
complaint layout optimization, including: (i) target layout T resulting in
printed image P(T) and (ii) a new target layout T' resulting in printed image
improved printed image P(T').

FIG. 6
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Côté explains that process compliant layout optimizations produce a new
target layout T', in which “layout T' shapes have been moved to improve
process latitude, specifically in the original layout T, the two features were a
distance d1 apart, but in the new target layout the features are a spaced
further apart.” (Col. 6, ll. 7–17.) Because Côté explains that: (i) design
rules 505 and local layout requirements 518 are fed into layout optimizer
520 and (ii) Figure 6 illustrates a new target layout T' resulting in improved
printed image P(T'), Côté teaches the limitation “combining said location
dependent modifications with said constraint relationships to form location
dependent constraint relationships.”
First, Patent Owner argues that following:
Côté does not teach or suggest a connection between
design rules 505, or any “constraint relationships” allegedly
generated from those design rules, and layout optimizer 520.
Côté’s Figure 5 shows design rules 505 being used once, in
layout creation process 503. Côté does not teach or suggest,
e.g., that design rules 505 are used a second time in connection
with layout optimizer 520, that any information from the layout
creation process 503 (other than layout 510) is provided to
layout optimizer 520, or that any “constraint relationships”
allegedly built in layout creation process 503 from the design
rules 505 are otherwise modified or combined in layout
optimizer 520. On the contrary, Côté teaches that layout
creation process 503 and layout optimization 520 are distinct,
sequential steps, with different inputs – layout creation process
503 receives design rules 505, while layout optimizer 520
receives local layout requirements 518.
(Appeal Br. 34.) Contrary to Patent Owner’s arguments, the Examiner
found that Figure 5 of Côté illustrates the interaction between design
rules 505, local layout requirements 518, and layout optimizer 520. (Final
Act. 29–30.) Even if Patent Owner is correct that layout creation 503 and
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layout optimizer 520 “are distinct, sequential steps, with different inputs,”
the claim limitations “building constraint relationships associated with said
initial design layout,” “formulating at least one location dependent
modification to said constraint relationships,” and “combining said location
dependent modifications with said constraint relationships to form location
dependent constraint relationships” are broad enough to encompass Figure 5
of Côté, a flow chart illustrating the steps employed to generate a layout.
Moreover, Patent Owner’s argument that “Côté’s Figure 5 shows design
rules 505 being used once” is not commensurate in scope with independent
claim 1, because this claim does not require the limitation “building
constraint relationships” to be used more than once.
Second, Patent Owner argues “Côté’s disclosure is consistent with the
understanding of a person of ordinary skill that layout optimizer 520 does
not receive any ‘constraint relationships’ that may be created as part of a
design rule check at the layout creation step 503.” (Appeal Br. 34.) To
support this argument, Patent Owner points to paragraph 19 of the Gupta
Declaration, which states the following:
In the EDA field, such layout creation process 503 would
be ordinarily implemented by a commercial tool that receives a
circuit design, such as a SPICE netlist or a VHDL file, and
outputs a layout, such as a GDS-II file. . . . Therefore, to the
extent any constraint relationships are built as part of layout
creation process 503, a person of ordinary skill in the art would
understand that those constraint relationships are entirely
internal to that software tool and would be discarded by the
time the layout optimizer 520 comes into play. It is also
important to note that, unlike layout creation process 503,
layout optimizer 520 does not receive design rules 505 as an
input.
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(¶ 19.) However, the statements in paragraph 19 of the Gupta Declaration
relied upon by Patent Owner lack persuasive factual support because the
Gupta Declaration does not cite to sufficient corroborating evidence. See In
re Beattie, 974 F.2d 1309, 1313 (Fed. Cir. 1992) (“[D]eclarations themselves
offer only opinion evidence which has little value without factual support.”).
Third, Patent Owner argues the following:
Côté provides no guidance as to how to implement the
layout optimizer 520 that would lead one of ordinary skill in the
art to modify and combine “constraint relationships associated
with said initial design layout” (which Côté undisputedly does
not disclose). Indeed, Côté discloses nothing about the
functionality, structure or operation of layout optimizer 520,
and cites no references explaining how layout optimizer 520
purportedly works. Nor does Côté explain what the local layout
requirements 518 are, and certainly does not teach that they are
in any way related to, modify, or are combined with the alleged
“constraint relationships associated with said initial design
layout.”
(Appeal Br. 36.) Again, the Examiner found that Figure 5 of Côté illustrates
the interaction between design rules 505, local layout requirements 518, and
layout optimizer 520, and thus, the obviousness rejection is not based on
modifying Côté. (Final Act. 29–30.) Moreover, Patent Owner’s arguments
are not commensurate in scope with independent claim 1, because this claim
does not require a description of functionality, structure, or operation with
respect to the limitation “combining said location dependent modifications
with said constraint relationships to form location dependent constraint
relationships.”
Fourth, Patent Owner argues that “Côté does not explain what, if any,
role is played by the design rules 505, or by any alleged ‘constraint
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relationships’ built from those design rules, in layout optimization” and “the
term ‘layout optimizer’ would encompass many different methodologies that
need not even operate on ‘constraint relationships.’” (Appeal Br. 36.) To
support this argument, Patent Owner points to paragraph 18 of the Gupta
Declaration, which states the following:
From my experience, many layout optimization
methodologies do not modify “constraint relationships,” but
rather directly modify layout objects according to rules that are
entirely independent from “constraint relationships.” There are
myriads of layout optimizers known in the field, from
compactors to OPC software tools. Some use constraint
relationships, some do not.
(¶ 18.) Patent Owner’s arguments are not persuasive because Patent
Owner’s declarant, Dr. Gupta, admits that “many layout optimization
methodologies do not modify ‘constraint relationships,’” but “[s]ome [layout
optimizers] use constraint relationships.”
Fifth, Patent Owner argues that
While Côté states that “additional constraints 518 feed into a
layout optimizer 520”, “Côté does not explain what those
‘additional constraints’ are, and what they are ‘additional’ to.”
Otherwise put, Côté’s “additional constraints” may be
additional, but they are not additive in the sense of meeting
limitations [c] “formulating at least one location dependent
modification to said constraint relationships” and [d]
“combining said location dependent modifications with said
constraint relationships to form location dependent constraint
relationships.” In fact, Côté’s “additional constraints” would be
understood as being independent from any “constraint
relationships associated with said initial design layout.”
(Appeal Br. 37 (emphases and citations omitted).) Similarly, Patent Owner
argues the following:
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The “new target layout T” shown in Côté’s Figure 6 could be
obtained in ways that do not involve “constraint relationships
associated with [an] initial design layout” or “location
dependent modification[ s] to said constraint relationships.”
As an example, . . . a person of ordinary skill in the art would
understand Côté’s “additional constraint[]” as a constraint that
forces the shape on the right-hand side of Fig. 6 to be at the
position shown in the “new target layout T',” without involving
any “constraint relationships” allegedly built during layout
creation.
(Appeal Br. 42–43.) To support these arguments, Patent Owner points to
paragraph 20 of the Gupta Declaration, which states the following:
To be clear, Côté states that “additional constraints 518
feed into a layout optimizer 520.” This indicates that the layout
optimizer 520 operates on some kind of “additional
constraints.” However, Côté does not explain what those
“additional constraints” are, and what they are “additional” to.
While Côté does not preclude feeding constraint relationships
from layout creation process 503 to layout optimizer 520, it
does not indicate so either.
(¶ 20 (citations omitted).) However, as found by the Examiner (Ans. 9, 12),
in the “Background” section, Côté explains that “the use of design rules can
lead to sub-optimal layouts” (col. 2, ll. 5–6) and “[i]t may be preferable to
use a larger spacing between shapes whenever possible to improve ‘process
latitude’” (col. 2, ll. 10–12). Thus, in the context of the “Background”
section of Côté, one of ordinary skill in the art would recognize that:
(i) “design rules that specify a number of constraints, such as minimum
spacings” (col. 1, ll. 59–60), which refers to design rule 505, is additive to
(ii) a preference “to use a larger spacing between shapes” (col. 2, ll. 10–12)
which refers to local layout requirements 518.
Last, Patent Owner argues the following:
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The Examiner’s rejection is premised on an incorrect
interpretation of the quantity d1 in Figure 6 as a minimum
spacing defining a “constraint relationship,” which is
contradicted by Côté’s teachings. What Côté actually teaches is
that the quantity d1 is a distance, and not a “constraint
relationship” that is modified by a “location dependent
modification.” In particular, Côté states: “Within this new
target layout T' shapes have been moved to improve process
latitude, specifically in the original layout T, the two features
were a distance d1 apart, but in the new target layout the
features are [] spaced further apart.”
(Appeal Br. 40 (citations omitted).) To support these arguments, Patent
Owner points to paragraph 13 of the Gupta Declaration, which states the
following:
Côté is clear that the quantity d1 is simply the actual distance
between two objects in the layout: “in the original layout T, the
two features were a distance d1 apart.” Côté does not teach that
d1 is the minimum spacing required between the two layout
objects dictated by a “constraint relationship,” or that it has
anything to do with a “constraint relationship.”
(¶ 13 (emphases and citation omitted).) Again, as found by the Examiner
(Ans. 12), in the “Background” section, Côté explains that “[a] layout of an
integrated circuit is typically created in accordance with a set of design rules
that specify a number of constraints, such as minimum spacings” (col. 1,
ll. 58–60) but “[i]t may be preferable to use a larger spacing between shapes
whenever possible to improve ‘process latitude’” (col. 2, ll. 10–12).
Contrary to Patent Owner’s arguments, in the context of the “Background”
section of Côté, one of ordinary skill in the art would recognize that:
(i) “design rules that specify a number of constraints, such as minimum
spacings” (col. 1, ll. 59–60) refers to target layout T from Figure 6 with two
features distance d1 apart; and (ii) “to use a larger spacing between shapes
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whenever possible to improve ‘process latitude’” (col. 2, ll. 10–12) refers to
new target layout T' from Figure 6 with two features greater than distance d1
apart.
Thus, we agree with the Examiner that Côté would have rendered
obvious the subject matter of independent claim 1, which includes the
limitations “building constraint relationships associated with said initial
design layout,” “formulating at least one location dependent modification to
said constraint relationships,” and “combining said location dependent
modifications with said constraint relationships to form location dependent
constraint relationships.”
We are unpersuaded by Patent Owner’s arguments (Appeal Br. 44–45;
see also Reply Br. 12) that Côté does not teach the limitation “implementing
said location dependent constraint relationships. . . in a manner that is
substantially in compliance with design rules,” as recited in independent
claim 1.
The Examiner found that layout optimizer 520 of Côté, which updates
an original layout to produce layout 522 with enhanced process latitude,
corresponds to the limitation “implementing said location dependent
constraint relationships, . . . in a manner that is substantially in compliance
with design rules.” (Final Act. 30; see also Ans. 12–13.) We agree with the
Examiner’s findings.
As discussed previously, in the “Background” section, Côté explains
that “[a] layout of an integrated circuit is typically created in accordance
with a set of design rules.” (Col. 1, ll. 58–59.) Also discussed previously,
Côté explains that “layout optimizer 520 attempts to update the layout to
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produce a layout 522 with enhanced process latitude” (col. 5, ll. 37–39), and
in reference to Figure 6, Côté explains that “layout T' shapes have been
moved to improve process latitude, specifically in the original layout T, the
two features were a distance d1 apart, but in the new target layout the
features are a spaced further apart” (col. 6, ll. 8–12). Because Côté explains
that a layout is set in accordance to design rules 505 and layout optimizer
520 attempts to update the layout by optimizing its design, Côté teaches the
limitation “implementing said location dependent constraint relationships
. . . in a manner that is substantially in compliance with design rules.”
Patent Owner argues that “Côté does not teach or suggest limitation
. . . ‘implementing said location dependent constraint relationships . . . in a
manner that is substantially in compliance with design rules’ in claim 1.”
(Appeal Br. 44.) In particular, Patent Owner argues that “[t]he relevant
question is whether Côté’s layout optimizer 520 enforces compliance with
design rules in the first place” and “nothing in Côté would teach or suggest
to a person of ordinary skill that layout optimizer 520 applies design rules
505 in any way.” (Id. at 45; see also Reply Br. 12.) To support these
arguments, Patent Owner points to paragraph 21 of the Gupta Declaration,
which states the following:
In the 2005 timeframe, layout hotspot fixing approaches
generally worked by generating process simulation based hints
(similar to Côté’s image analyzer). Checking against other
constraints (e.g., design rules) was left to the designer. Even a
person with more than ordinary skill in the art in the 2005
timeframe would understand Côté’s layout optimizer to be such
a tool that generates correction hints to address yield concerns,
without combining them with constraint relationships existing
in the original design.
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(¶ 21.) As found by the Examiner, and contrary to Patent Owner’s
arguments, Côté explains that “layout optimizer 520 attempts to update the
layout to produce a layout 522 with enhanced process latitude” (col. 5,
ll. 37–39), such that “[a] layout of an integrated circuit is typically created in
accordance with a set of design rules [505]” (col. 1, ll. 58–59). Again, the
statements in paragraph 21 of the Gupta Declaration relied upon by Patent
Owner lack persuasive factual support because the Gupta Declaration does
not cite to sufficient corroborating evidence. See Beattie, 974 F.2d at 1313
(“[D]eclarations themselves offer only opinion evidence which has little
value without factual support.”).
Thus, we agree with the Examiner that Côté would have rendered
obvious the subject matter of independent claim 1, which includes the
limitation “implementing said location dependent constraint relationships
. . . in a manner that is substantially in compliance with design rules.”
Accordingly, we sustain the Examiner’s rejection of independent
claim 1 under 35 U.S.C. § 103(a).
Independent claim 9 recites limitations similar to those discussed with
respect to independent claim 1, and Patent Owner has not presented any
additional substantive arguments with respect to this claim. We sustain the
Examiner’s rejection of independent claim 9 for the same reasons discussed
with respect to independent claim 1.

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DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 9, 11 103(a) Allan 1, 9, 11
2, 4, 10, 12 103(a) Allan, Lukanc 2, 4, 10, 12
5 103(a) Allan, Bamji 5
6, 7, 14 103(a) Allan, Balasinski 6, 7, 14
1, 9 103(a) Côté 1, 9
2, 4, 10, 12 103(a) Côté, Lukanc 2, 4, 10, 12
11 103(a) Côté, Kroyan 11
5 103(a) Côté, Bamji 5
6, 7, 14 103(a) Côté, Balasinski 6, 7, 14
Overall
Outcome
1, 2, 4–7, 9–
12, 14

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

PATENT OWNER:
KING & WOOD MALLESONS LLP
500 FIFTH A VENUE
50TH FLOOR
NEW YORK, NY 10110