Ex Parte SEKODownload PDFPatent Trial and Appeal BoardJul 28, 201612730859 (P.T.A.B. Jul. 28, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 121730,859 03/24/2010 130036 7590 08/01/2016 Stoel Rives LLP Attn: Longitude Licensing [54361] [74735] 201 South Main Street, Suite 1100, One Utah Center Salt Lake City, UT 84111 Akiyoshi SEKO UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. Ql 18050 9974 EXAMINER RAABE, CHRISTOPHER M ART UNIT PAPER NUMBER 2879 NOTIFICATION DATE DELIVERY MODE 08/01/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): joe.hawkins@stoel.com slcpatent@stoel.com j anet. wilson@stoel.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte AKIYOSHI SEKO Appeal2015-000922 Application 12/730,859 Technology Center 2800 Before TERRY J. OWENS, CHRISTOPHER C. KENNEDY, and JENNIFER R. GUPTA, Administrative Patent Judges. GUPTA, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's decision2 finally rejecting claims 19--40. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 Appellant identifies the real party in interest as Elpida Memory, Inc. Appeal Brief filed April 7, 2014 ("App. Br."), 2. 2 Final Office Action mailed November 7, 2013 ("Final Act."). Appeal2015-000922 Application 12/730,859 The claims are directed to a semiconductor memory device. Spec. 1, 11. 10. Claim 19, reproduced below with the disputed claim terms in italics, is illustrative of the claims on appeal. 19. A device comprising: a plurality of bit lines each extending in a first direction, the bit lines being arranged substantially in parallel to one another in a second direction crossing the first direction so that the bit lines include odd-numbered bit lines and even-numbered bit lines in the second direction; a plurality of memory elements each coupled to an associated one of the odd-numbered and even-numbered bit lines; a reference line; a first sense amplifier including first and second input terminals, the second input terminal being coupled to the reference line; a second sense amplifier including third and fourth input terminals, the fourth input terminal being coupled to the reference line; a plurality of first switches each including first and second nodes, the first nodes of the first switches being coupled in common to the first input terminal of the first sense amplifier, and the second nodes of the first switches being coupled to the odd-numbered bit lines, respectively; a plurality of second switches each including third and fourth nodes, the third nodes of the second switches being coupled in common to the third input terminal of the second sense amplifier, and the fourth nodes of the second switches being coupled to the even-numbered bit lines, respectively; a voltage line; a third switch coupled between the voltage line and the first input terminal of the first sense amplifier; and a fourth switch coupled between the voltage line and the third input terminal of the second sense amplifier. 2 Appeal2015-000922 Application 12/730,859 REJECTIONS ON APPEAL 1. Claims 19-29, 31-33, and 38--40 stand rejected under 35 U.S.C. § 102(b) as anticipated by Koyama (US 200710171693 Al, published July 26, 2007) (hereinafter "Koyama"); and 2. Claims 30 and 34--37 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Koyama in view of Chi et al. (US 5,870,343, issued Feb. 9, 1999) (hereinafter "Chi"). ANALYSIS In view of the evidence of record and the findings and arguments set forth in the Final Action, the Appeal Brief, the Answer, and the Reply Brief, we determine that the Appellant has shown reversible error in the rejection, which we reverse. We need address only the sole independent claim, i.e., claim 19. "A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference." Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987). Anticipation by inherency requires that any material missing from the prior art must necessarily be present in the reference. In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999). "Inherency, however, may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient." In re Oelrich, 666 F.2d 578, 581(CCPA1981) (quotingHansgirgv. Kemmer, 102 F.2d 212, 214 (CCPA 1939)). The Examiner finds that Koyama anticipates claim 19. The Examiner relies on Koyama's Figure 7 for disclosing, inter alia, a device comprising a 3 Appeal2015-000922 Application 12/730,859 plurality of bit lines (odd-numbered bit lines 713, even-numbered bit lines 714), a first sense amplifier (719) including first and second terminals not labeled), a second sense amplifier (720) including third and fourth terminals (not labeled), a plurality of first switches (723) each including first and second nodes, the first nodes of the first switches being coupled in common to the first input terminal of the first sense amplifier (719), and the second nodes of the first switches being coupled to the odd-numbered bit lines (713), and a plurality of second switches (724) each including third and fourth nodes, the third nodes of the second switches being coupled in common to the third input terminal of the second sense amplifier (720), and the fourth nodes of the second switches being coupled to the even-numbered bit lines (714). Examiner's Answer mailed August 22, 2014 ("Ans."), 2-3. Koyama discloses a first switch (723) including one first node and one second node where the first node is coupled to the first input terminal of the first sense amplifier (719) and the second node is coupled to an odd- numbered bit line (713). Koyama i-fi-175, 77; Fig. 7. Koyama discloses a second switch (724) including one third and one fourth node where the third node is coupled to the third input terminal of the second sense amplifier (720). Id. However, as the Appellant argues, Koyama does not disclose or suggest a plurality of switches (723) each including first and second nodes where the first node.§. (e.g., two or more nodes) are "coupled in common to the first input terminal of the first sense amplifier" and two or more second node.§. of the first switches are "coupled to the odd-numbered bit line.§.." App. Br. 7-8. Likewise, although Koyama discloses a second switch (724) including a third and a fourth node, Koyama does not disclose or suggest f!: plurality of second switches (724) each including third and fourth nodes 4 Appeal2015-000922 Application 12/730,859 where the third node§. (e.g., two or more nodes) are "coupled in common to the third input terminal of the second sense amplifier" and two or more fourth node§. are "coupled to the even-numbered bit line§.." Id. at 9-10. Even though Koyama's Figure 7 includes only two bit lines, the Examiner asserts that Koyama describes embodiments with additional bit lines (e.g., Koyama i-fi-17, 16; Fig. 12A), and using additional bit lines in Koyama's Figure 7 will inherently result in a device having the structure of the device recited in claim 19. Ans. 12. However, as the Appellant argues, the Examiner has not shown that if Koyama's Figure 7 uses additional bit lines, the first nodes of the first switches would necessarily be coupled to the same first input terminal of the same sense amplifier (719) and the third nodes of the second switches would necessarily be coupled to the same input terminal of the same second sense amplifier (720). See Reply Brief filed October 22, 2014 ("Reply Br."), 4---6; see also Koyama Fig. 5 (where the nodes are connected to different inputs of a sense amplifier (e.g., 529)). For the reasons above, the Examiner has not established that Koyama discloses, expressly or inherently, every limitation of claim 19. Accordingly, we reverse the anticipation rejection of claims 19-29, 31-33, and 38--40. The Examiner relies upon the factual findings made in the anticipation rejection to support the obviousness rejection of claims 30 and 34--37. Ans. 10-11. Because the anticipation rejection is based on erroneous factual findings, as discussed above, we reverse the obviousness rejection of claims 30 and 34--37. 5 Appeal2015-000922 Application 12/730,859 DECISION We REVERSE the rejection of claims 19-29, 31-33, and 38--40 under 35 U.S.C. § 102(b) as being anticipated by Koyama. We REVERSE the rejection of claims 30 and 34--37 under 35 U.S.C. § 103(a) as being unpatentable over Koyama and Chi. REVERSED 6 Copy with citationCopy as parenthetical citation