Ex Parte Monchiero et alDownload PDFPatent Trial and Appeal BoardApr 30, 201412366234 (P.T.A.B. Apr. 30, 2014) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte MATTEO MONCHIERO, JACOB B. LEVERICH, PARTHASARATHY RANGANATHAN, NORMAN PAUL JOUPPI, and VANISH TALWAR ____________________ Appeal 2012-002887 Application 12/366,234 Technology Center 2800 ____________________ Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF CASE Appellants seek review of the Examiner’s decision to reject claims 1-6 and 16-20. We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a). We AFFIRM. The claims are directed to an integrated circuit package with an interposer inserted between a digital logic die and a substrate (claim 1; Spec. ¶ 0022). The interposer die includes at least one transistor (claim 1). Appeal 2012-002887 Application 12/366,234 2 Figure 4A illustrates an example of the integrated circuit package, and is reproduced below: Figure 4A is a cross-sectional diagram of integrated circuit package 400 The integrated circuit package 400 of Figure 4A includes an interposer die 405 stacked between a digital logic die 420 and a substrate 415 (Spec. ¶¶ 0037-38). The interposer die 405 includes transistors (unlabeled in Fig. 4A) (Spec. ¶ 0038). Figure 4B provides a close-up view of one the transistors 410 within the interposer, and is reproduced below: Appeal 2012-002887 Application 12/366,234 3 Figure 4B is a cross-sectional diagram of a part of the interposer die of Figure 4A The transistor shown in Figure 4B is a vertically oriented MOSFET sleep transistor (Spec. ¶ 0039). To illustrate the invention being claimed, we reproduce claim 1 below, with reference numerals taken from Figures 4A and 4B: 1. An integrated circuit package comprising: a digital logic die [420] disposed on a substrate [415]; and an interposer die [405] stacked vertically with said digital logic die [420] on said substrate [415]; wherein said interposer die [405] comprises at least one transistor [410] configured to selectively provide electrical power to a portion of said digital logic die. (Claims App’x at Br. 15.) We note that claim 1 does not specifically limit the transistor to a vertically oriented MOSFET sleep transistor. Appeal 2012-002887 Application 12/366,234 4 Claims 1, 2, 4-6, and 16-19 are rejected under 35 U.S.C. §103(a) as obvious over the combination of Bohr1 and Vandentop2; and claims 3 and 20 are rejected over those prior art references further in view of additional evidence of obviousness (Br. 7). OPINION A. Obviousness over Bohr and Vandentop With respect to the rejection of claims 1, 2, 4-6, and 16-19 under 35 U.S.C. § 103(a) as obvious over the combination of Bohr and Vandentop, Appellants’ arguments raise issues with respect to the rejection of claims 1, 5, 6, and 18. We thus select those claims as representative. 1. Claim 1 With regard to the rejection of claim 1, the issue on appeal is whether the Examiner reversibly erred in finding that Bohr’s interposer die includes “at least one transistor configured to selectively provide electrical power to a portion of said digital logic die” as recited in claim 1 (compare Ans. 4-5 and 8-9 with Br. 8-11 and Reply Br. 4-8). There is no question that Bohr teaches an interposer die including a transistor as shown in Bohr’s Figure 6. Figure 6 is reproduced below: 1 Bohr, US 6,617,681 B1, patented Sep. 9, 2003. 2 Vandentop et al., US 6,580,611 B1, patented Jun. 17, 2003. Appeal 2012-002887 Application 12/366,234 5 Figure 6 is a schematic cross-section of a silicon-based interposer This interposer replaces the Organic Land Grid Array (OLGA) package 104 shown in Figure 1 (Bohr, col. 1, l. 60 to col. 2, l. 4). Figure 1 is reproduced below: Figure 1 is a schematic side-view showing the interposer inserted between the die and printed circuit board Solder bumps 106 and solder balls 110 electrically connect the circuit within integrated circuit die 102 to a circuit within the printed circuit board Appeal 2012-002887 Application 12/366,234 6 108 by way of metal lines (Cu Damascene interconnects) and vias within the interposer/OLGA package 104 (Bohr, col. 5, ll. 40-60; Fig. 2). Bohr replaces the prior art OLGA with a silicon interposer (Bohr, col. 4, ll. 6-10). At the time of Bohr’s invention, OLGA packages could not be used to make transistors and were not conducive to forming certain types of capacitors (Bohr, col. 3, ll. 51-59). But the use of a silicon substrate allows the integration of circuit elements into the interposer including “the integration of passive circuit elements, such as capacitors, and active circuit elements, such as transistors.” (Bohr, col. 4, ll. 19-28.) Bohr states that “[b]y integrating various active and passive circuit elements into the interposer, it is possible to include circuit functionality into the interposer.” (Bohr, col. 6, ll. 63-65). Bohr then offers examples, including power regulation circuits (Bohr, col. 7, l. 5). Bohr teaches integrating capacitors 130 and 134 (134 labeled a decoupling capacitor in Fig. 5) into the interposer and integrating transistor 140 (labeled MOS transistor in Fig. 6) into the interposer (Bohr, col. 6, ll. 27-51). The Examiner acknowledges that Bohr does not specifically state that the transistor is “configured to selectively provide electrical power to a portion of said digital logic die” (Ans. 8-9). Instead, the Examiner finds that Bohr suggests using an insulated gate field effect transistor operating, for example, at a second range of voltages as transistor 140 within the interposer (Ans. 9). According to the Examiner such a transistor is capable of selectively providing electrical power to a portion of said digital logic die, and as such has the structure required by claim 1 (id.). Appeal 2012-002887 Application 12/366,234 7 Appellants acknowledge that Bohr mentions “power regulation circuits.” (Br. 9). Appellants contend that “Bohr does not ever actually teach or suggest ‘wherein said interposer die comprises at least one transistor configured to selectively provide electrical power to a portion of said digital logic die’” but “[t]o the contrary, Bohr actually teaches using capacitors to make a power connection between the die and the interposer.” (Br. 9.) Appellants cite to claim 7 of Bohr, which is directed to an electronic assembly with an interposer containing a power supply node coupled to one terminal of a capacitor and another power supply node coupled to another terminal of the capacitor (Bohr, claim 7). Appellants contend that this is a teaching away from the claimed subject matter (Br. 10). Claim 7 of Bohr, however, does not provide any particular teaching with regard to transistors, and other portions of Bohr are more expansive in their teachings. Bohr as a whole contemplates using capacitors and transistors for their known functions, and does not specifically limit power regulation to the use of capacitors. We cannot say that Bohr teaches away from using transistors “configured to selectively provide electrical power to a portion of said digital logic device.” On the other hand, Bohr does not specifically teach a transistor that is configured to do what the claim recites, the reference merely generally states that active and passive elements that regulate power can be used in the interposer circuit (col. 6, l. 63 to col. 7, l. 10). The ultimate question is: Does Bohr teach or suggest a transistor having the structure required by the claim? It has long been held that “apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 Appeal 2012-002887 Application 12/366,234 8 F.2d 1464, 1468 (Fed. Cir. 1990). An inventor of a structure (machine or article of manufacture) is entitled to benefit from all of its uses, even those not described, Roberts v. Ryer, 91 U.S. 150, 157 (1875), and conversely, patentability of the structure cannot turn on the use or function of the structure. In re Michlin, 256 F.2d 317, 320 (CCPA 1958) (“It is well settled that patentability of apparatus claims must depend upon structural limitations and not upon statements of function.”). Therefore, the courts have devised a test: Structures such as machines and articles of manufacture must be distinguished from the prior art on the basis of structure, and where there is reason to believe that the structure of the prior art is inherently capable of performing the claimed function, the burden shifts to the applicant to show that the claimed function patentably distinguishes the claimed structure from the prior art structure. See In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997); In re Hallman, 655 F.2d 212, 215 (CCPA 1981). The Examiner has applied this basic test to the claims before us and determined that Bohr teaches an insulated gate field effect transistor (IGFET) operating, for example, at a second range of voltages (Ans. 9.). And further found that such IGFETs are “capable of selectively providing electrical power to the portion of said digital logic die.” (Id.) On this basis the Examiner determines that Bohr’s transistor meets the structural requirements of the claim limitation (id.). Appellants contend that “it is specious to suggest, as does the Action, that the structure of Bohr is capable of performing like the claimed integrated circuit package” because “Bohr does not ever actually teach or suggest that those transistors are ‘configured to selectively provide electrical Appeal 2012-002887 Application 12/366,234 9 power to a portion of said digital logic die.’ (Claim 1) (emphasis added) (Br. 10). But, as pointed out by the Examiner, Appellants do not provide any evidence or reason why Bohr’s transistor would not be capable of functioning as recited in the claim (Ans. 9). Bohr need not actually use the language of Appellants’ claim to teach a transistor of a structure having the claimed capability. Appellants further contend that the Examiner has failed to understand the concept of “intended use” and on this basis mischaracterizes the claim (Reply Br. 5-6). According to Appellants, “[t]he recitation that at least one transistor is "configured to selectively provide electrical power to a portion of said digital logic die" necessarily applies to the structure of the claimed device (id.). Appellants reason that: A transistor, alone in a vacuum, could not be the claimed transistor because such a transistor would lack the supporting structure, e.g., connections to other circuit components, the "configuration," to allow it to perform as claimed. If we recited the aspiration of using that transistor, alone in a vacuum, to provide power to a digital logic die selectively, that would be a statement of intended use. It is not a statement of intended use to instead, as claim 1 does, recite that the transistor is incorporated into an integrated circuit package with the necessary configuration to perform a specifically cited function. (Reply Br. 6.) Herein lies the crux of the dispute between the Appellants and the Examiner. Appellants appear to believe the claim language modifying the transistor applies to more than just the transistor, while the Examiner determines that the modifying language only relates to the transistor itself (compare Ans. 8-9 with Reply Br. 5-7). This leads us to an issue of claim interpretation. Appeal 2012-002887 Application 12/366,234 10 Interpreting claim 1 as broadly as is reasonable and consistent with the Specification, we determine that the language “configured to selectively provide electrical power to a portion of said digital logic die” only modifies “at least one transistor.” The phrase “configured to selectively provide electrical power to a portion of said digital logic die” refers only to the “at least one transistor;” it does not refer to a circuit including the transistor or connections to other circuit components. The Examiner’s finding that an IGFET operating at different voltages than the transistors in the die is capable of functioning as required by claim 1 is reasonable and the burden was shifted to Appellants to show that, in fact, the prior art transistor would not have the claimed function. Appellants have not met that burden. After weighing the evidence and arguments and considering the evidence in light of the relevant law, we determine that a preponderance of the evidence supports the Examiner’s rejection of claim 1. 2. Claim 5 Claim 5 reads as follows: 5. The integrated circuit package of claim 1, wherein a gate of said at least one transistor is electrically coupled to at least one of: a processor core implemented in said logic die and separate power management control circuitry implemented in said logic die. (Claims App’s at Br. 15.) The Examiner finds that Bohr’s transistor 140 has a gate 144 electrically connected to the digital logic die 102 (Ans. 10). Appeal 2012-002887 Application 12/366,234 11 Appellants contend that the portions of Bohr cited by the Examiner do not mention electrically coupling the transistor gate as claimed (Br. 11-12; Reply Br. 8-10). As shown in Figure 1, reproduced below, Bohr teaches an interposer 104 containing circuits electrically coupled to a silicon die 102 by means of solder bumps 106 (Bohr, col. 5, ll. 41-45). The circuits within the interposer include transistors 140 (Bohr, Fig. 6; col. 6, ll. 48-51). These transistors include gates 144 (Bohr, Fig. 6; col. 6, ll. 51-54). Bohr does not disclose a terminal to the gate 144, but the gate is part of the electric circuit running from the solder bumps on the top of the interposer through the Cu Damascene interconnections and Cu via to the solder ball on the bottom of the interposer (Fig. 6). The question is whether the gate is “electrically coupled” to the silicon die 102 by virtue of its presence in the transistor or whether “electric coupling” requires a direct connection of the interconnect to an electrical terminal on the gate. Neither Appellants nor the Examiner provide us with evidence of the meaning of “electrically coupling” within the art. According to Dictionary.com, in the context of electricity, “coupling” is defined as “the association of two circuits or systems in such a way that power may be transferred from one to the other.” Our review of the Specification turns up no special definition for “electrically coupling” contrary to the meaning recited in Dictionary.com. Interpreting “electrically coupling” as broadly as is reasonable and consistent with the meaning one of ordinary skill in the art would give the terms, we determine that “electrically coupling” includes the type of electrical connection present between the gate of Bohr’s transistor and the Appeal 2012-002887 Application 12/366,234 12 other components of the circuit linking the transistor of the interposer to the circuit within the silicon die through the solder bumps. Appellants have not convinced us of reversible error in the Examiner’s rejection of claim 5. 3. Claim 6 Claim 6 reads: 6. The integrated circuit package of claim 1, wherein said interposer die comprises at least one via that electrically couples said at least one signal from said substrate to said digital logic die. (Claims App’x at Br. 16.) In response to Appellants’ argument that the Examiner failed to indicate how or where Bohr teaches the via required by claim 6 (Br. 12), the Examiner finds: Bohr teaches said interposer die (115, an interposer in fig. 6) comprising at least one via (an electrically conductive via formed of Cu) that electrically couples said at least one signal (Abstract, particularly “[e]lectrically conductive vias provide signal pathways between the first surface and the second surface of the interposer”) from said substrate (108, a printed circuit board electrically connected with the interposer in figs. 1, 6, col. 5, lines 49-51) to the digital logic die (102, a silicon die electrically connected with the interposer in figs. 1,6, col. 5, lines 43-45 in view of Vandentop teaching a microelectronic device 4 such as a microprocessor in fig. 3 & col. 1, lines 20- 24). (Ans. 10.) Figure 6 shows the vias (Cu vias) within the interposer die. The vias are electrically connected to the substrate and die through interconnects and solder bumps and balls as shown in Figures 1 and 6. The Examiner’s Appeal 2012-002887 Application 12/366,234 13 findings are reasonable and Appellants do not dispute those findings in the Reply Brief. Appellants have not convinced us of reversible error in the Examiner’s rejection of claim 5. 4. Claim 18 Claim 18 reads: 18. The integrated circuit package of claim 1, wherein said interposer die comprises a plurality of transistors electrically connected to a logic device of said digital logic die, said transistors selectively providing electrical power to said logic device of said digital logic die. (Claims App’x at Br. 17.) In response to Appellants’ argument that the Examiner failed to indicate how or where the cited references teach what is claimed (Br. 12-13), the Examiner reproduces the finding that Bohr teaches the via and electrical pathways of claim 6 (reproduced above) and then states that “the recitation of ‘said transistors selectively providing electrical power to said logic device of said digital logic die’ is an intended use.” The Examiner finds that Bohr teaches operating the interposer die transistors at a second range of voltages and such transistors are capable of selectively providing electrical power to the logic gate device of the digital logic die (Ans. 11). Appellants contend that: As demonstrated above, the cited references do not, in fact, teach or suggest even a single transistor that is “selectively providing electrical power to said logic device of said digital logic die.” (Claim 18). Thus, the cited reference further do not teach or suggest the claimed plurality of transistor “electrically connected to a logic device of said digital logic die, said transistors selectively providing electrical power to said logic Appeal 2012-002887 Application 12/366,234 14 device of said digital logic die.” (Claim 18). Consequently, the rejection of claim 18 should not be sustained. (Reply Br. 10.) Bohr’s Figure 6 depicts two transistors 140. Those transistors are electrically connected to the die 102 through interconnects and bumps. Appellants have not challenged the finding that Bohr teaches operating the transistors at a second range of voltages. Such a transistor would reasonably be capable of selectively providing power as claimed. The burden shifted to Appellants to show that, in fact, the structure is patentably different. Appellants have not addressed the Examiner’s finding that the prior art transistor is capable of functioning as claimed or otherwise overcome the Examiner’s finding of structural similarity. A preponderance of the evidence supports the Examiner’s rejection. B. The Rejections of Claims 3 and 20 The Examiner rejects claims 3 and 20 over Bohr and Vandentop and further in view of additional prior art references. Appellants contend that these rejections should not be sustained for at least the same reasons given above in favor of the patentability of claim 1 (Br. 13). For the reasons we state above, Appellants have not convinced us that the Examiner reversibly erred in rejecting claims 3 and 20. CONCLUSION We sustain the Examiner’s rejections. DECISION The Examiner’s decision is affirmed. Appeal 2012-002887 Application 12/366,234 15 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). 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