Ex Parte Eckert

Patent Trial and Appeal Board

Oct 29, 2013

11821065 (P.T.A.B. Oct. 29, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/821,065 06/21/2007 Wieland Eckert 2006P07029US 5789
22116 7590 10/30/2013
SIEMENS CORPORATION
INTELLECTUAL PROPERTY DEPARTMENT
170 WOOD AVENUE SOUTH
ISELIN, NJ 08830
EXAMINER
FENNEMA, ROBERT E
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
10/30/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte WIELAND ECKERT
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Appeal 2011-004716
Application 11/821,065
Technology Center 2100
____________

Before DEBRA K. STEPHENS, BRUCE R. WINSOR, and
CATHERINE SHIANG, Administrative Patent Judges.

SHIANG, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 10-13, 17-22, and 24-27. We have jurisdiction under 35
U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
The present invention relates to processing streaming data in a
multiprocessor system. See generally Spec. 1. Claim 10 is illustrative:
10. A method for processing streaming data in a multiprocessor
system having a pipelining architecture, comprising:
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inputting a plurality of data packets at an input time;
distributing the plurality of data packets between a plurality of
processors where the data packets remain during the processing;
supplying programs to the plurality of processors by pipelining
wherein individual programs are routed to individual ones of the plurality of
processors in a time sequence so that each in the plurality of processors
executes multiple programs on data packets which remain on that processor
in accord with the time sequence; and
outputting processed data packets at an output time.

THE REJECTIONS
Claims 10-13 and 17-21 are rejected under 35 U.S.C. §102(b) as being
anticipated by Catlin (U.S. 4,873,656). See Ans. 4-6.
Claims 22 and 24-27 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Catlin and Official Notice. See Ans. 7-9.

ISSUES
1. Under 35 U.S.C. § 102, has the Examiner erred by finding that Catlin
discloses “supplying programs to the plurality of processors by pipelining
wherein individual programs are routed to individual ones of the plurality
of processors in a time sequence so that each in the plurality of
processors executes multiple programs on data packets which remain on
that processor in accord with the time sequence” as recited in claim 10?
1

2. Has the Examiner erred by rejecting claim 22 because claims 22 recites
“a plurality of processors comprising a plurality of programs that process

1
Claim 10 (and similarly, claim 22) lacks antecedents for the recited
“individual programs” and “multiple programs.”

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data packets associated with the plurality of medical images”?
(Emphasis added).

ANALYSIS
Claim 10
On this record, we find that the Examiner did not err in rejecting claim
10.
Appellant argues that Catlin does not disclose the disputed claim
limitation. See App. Br. 6-10; Reply Br. 2-4. Appellant further argues that
Catlin does not teach any form of pipelining. See App. Br. 10. Appellant
also argues that Catlin does not teach the multiple programs that are
executed on each processor are routed to the processor. See App. Br. 9-10.
Appellant further contends that the rejections do not distinguish the recited
data packets from the recited programs. See App. Br. 8. Appellant also
argues that Catlin’s hardwired processors are hardwired and “[n]or is it clear
that any information (data) is sent to the hardwired processors to program
the processors.” See App. Br. 8; see also Reply Br. 4.
We disagree with Appellant’s arguments. The Examiner correctly
finds that Catlin teaches that the master processor distributes the circuit
elements (mapped to the recited supplying programs) to be simulated to
various processors (mapped to the recited plurality of processors). See Ans.
4-5, 14; Catlin, col. 2, ll. 35-39. We also adopt the Examiner’s reasoning
and findings on page 14 of the Answer as our own. See Ans. 14.
The Examiner further finds that Catlin teaches:
Prior to each processing cycle, information [such as circuit
elements] is passed along the unidirectional ring bus to the
various module units in information packets.
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See Catlin, col. 2, ll. 43-45; see also Ans. 4-5.

Thus, Catlin teaches that prior to each processing cycle
(mapped to the recited in a time sequence), distributing the circuit
elements to various processors by the ring bus (mapped to the recited
by pipelining, wherein individual programs are routed to individual
ones of the plurality of processors in a time sequence). See Ans. 4-5,
14-15. We also adopt the Examiner’s reasoning and findings on pages
11, 12, 14, and 15 of the Answer as our own. See Ans. 11-12, 14-15.
Our interpretation of pipelining is also consistent with the
Specification. See Spec. 2, ll. 1-14 and Spec. 7, ll. 7-15.

The Examiner also finds that Catlin teaches:
Once the input information for the various circuit
elements are placed in to the various processors, computation of
the various inputs associated with the circuit elements are
computed for this given time cycle. The results of the
computation determine the output from the various circuit
elements and these are stored within the processors. The
accelerator then is prepared to advance to the next time cycle to
utilize the stored outputs as inputs to the next stage of the
circuit.

Catlin, 2:60-68 (emphases added); see also Ans. 4-5.

Therefore, Catlin teaches that each in the the plurality of processors
executes the circuit elements (mapped to the recited multiple programs) on
the information input for the various circuit elements (mapped to the recited
data packets which remain on that process) for this given time cycle
(mapped to the recited in accord with the time sequence). See Ans. 4-5.
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Contrary to Appellant’s argument, the Examiner also correctly
distinguishes the recited data packets from the recited programs: Catlin
teaches the information input for the various circuit elements (mapped to the
recited data packets) are distributed to the various processors by the ring bus.
See Ans. 4-5; Catlin, 2:43-61. In contrast, as discussed above, the Examiner
maps Catlin’s circuit elements to the recited programs.
Finally, as pointed out by the Examiner, Appellant’s argument about
“hardwired” processors do not negate the Examiner’s findings, as Appellant
does not dispute that Catlin’s software processors are programmed. See
Ans. 13. Catlin discloses that “[t]he actual number of HPs 32 and SPs
[software processors] 31within a given module 22 is left to the design
choice of the designer.” See Catlin, col. 7, ll. 51-53 (emphasis added); see
also Ans. 13. Therefore, it is undisputed that Catlin’s software processors
can be mapped to the recited plurality of processors. See Ans. 13.
Accordingly, we sustain the Examiner’s rejection of claim 10.

Claims 11-13 and 17-21

Regarding claims 11-13, Appellant has not presented sufficient
evidence to persuade us of error. We disagree with Appellant’s arguments,
and agree with the Examiner’s conclusions. We adopt the Examiner’s
reasoning and findings as our own. See Ans. 5, 15.
Regarding claim 17, for similar reasons discussed above with respect
to claim 10, Appellant’s argument about program pipelining is unpersuasive.
Further, Appellant asserts that “there is no disclosure of control over
program pipelining by a control entity.” App. Br. 11. Appellant’s
conclusory assertion has little persuasive weight. Cf. 37 C.F.R.
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§ 41.37(c)(1)(vii) (2010) (“A statement which merely points out what a
claim recites will not be considered an argument for separate patentability of
the claim.”). We agree with the Examiner’s conclusions, and adopt the
Examiner’s reasoning and findings as our own. See Ans. 5.
Regarding claim 18, Appellant asserts that “[the rejection] presumes
that the Catlin reference discloses a higher level control entity for program
pipelining. It does not.” App. Br. 12. Appellant’s conclusory assertion
does not amount to an argument, and has little persuasive weight: Appellant
does not explain why that is the case, let alone show error in the Examiner’s
rejection. We agree with the Examiner’s conclusions, and adopt the
Examiner’s reasoning and findings as our own. See Ans. 5-6, 15.
Appellant does not separately argue claim 19.
Regarding claim 20, Appellant asserts that Catlin “does not refer to a
time difference.” App. Br. 12. We find the conclusory assertion
unpersuasive. Cf. 37 C.F.R. § 41.37(c)(1)(vii). We note that the cited Catlin
passage teaches time cycles and therefore, time difference. Appellant’s
remaining assertion is also unpersuasive for the reasons stated by the
Examiner. See Ans. 6, 16. We agree with the Examiner’s conclusions, and
adopt the Examiner’s reasoning and findings as our own. See id.
Regarding claim 21, Appellant does not present sufficient argument
(see App. Br. 12) and therefore, has not persuaded us of error. We agree
with the Examiner’s conclusions, and adopt the Examiner’s reasoning and
findings as our own. See Ans. 6, 16.
Accordingly, we sustain the Examiner’s rejection of claims 11-13 and
17-21.

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Claims 22 and 24-27
Claims 22 recites “a plurality of processors comprising a plurality of
programs that process data packets associated with the plurality of medical
images. . . .” (Emphasis added).
2

Appellant contends that one skilled in the art would not have been
motivated to process medical images in Catlin’s device because Catlin
implements an event driven simulation algorithm system that would not
have been used for processing x-ray images. See App. Br. 13-14.
We disagree with Appellant’s arguments, and agree with the
Examiner’s conclusion. We adopt the Examiner’s reasoning and findings on
pages 8 and 16-17 of the Answer as our own. See Ans. 8, 16-17. We
highlight the Examiner does not rely on Catlin’s for teaching simulation.
Although not relied on in affirming the rejection, we further note that
Appellant’s arguments are unpersuasive because the recited “medical
images” are non-functional descriptive material. The recited “medical
images” merely label the data packets, and do not functionally affect the
recited claim limitation of “a plurality of processors comprising a plurality
of programs that process data packets” or the processing system itself.
Therefore, the recited “medical images” are analogous to the instructions in
In re Ngai. See In re Ngai, 367 F.3d 1336, 1339 (Fed. Cir. 2004) (holding
the instructions are non-functional descriptive matter). As a result, the
recited “medical images” constitute non-functional descriptive material, and
“will not distinguish the invention from the prior art in terms of
patentability.” Id.; see also Ex parte Nehls, 88 USPQ2d 1883, 1887-89

2
Appellant does not contend that the preamble of claim 22 is limiting.
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(BPAI 2008) (precedential) (discussing cases pertaining to non-functional
descriptive material).
As to Appellant’s remaining arguments, for similar reasons discussed
above with respect to claim 10, we sustain the Examiner’s rejection of claim
22, and claim 25, which Appellant does not separately argue.
For similar reasons discussed above with respect to claims 12, 20, and
21, we sustain the Examiner’s rejection of claims 24, 26, and 27.

DECISION
The Examiner’s decision rejecting (1) claims 10-13 and 17-21 under
35 U.S.C. § 102, and (2) claims 22 and 24-27 under 35 U.S.C. § 103 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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