Ex Parte Assarpour

Patent Trials and Appeals Board

Mar 26, 2019

14041751 - (D) (P.T.A.B. Mar. 26, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/041,751 09/30/2013
136582 7590 03/28/2019
STEVENS & SHOWALTER, LLP
Box AVAYA Inc.
7019 Corporate Way
Dayton, OH 45459-4238
FIRST NAMED INVENTOR
Hamid Assarpour
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
913025-US-NP/AVA254PA 4644
EXAMINER
WARREN, TRACY A
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
03/28/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
pto@sspatlaw.com
pair_avaya@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HAMID ASSARPOUR
Appeal 2018-002486
Application 14/041, 7 51 1
Technology Center 2100
Before CARL W. WHITEHEAD JR., IRVINE. BRANCH, and
JOSEPH P. LENTIVECH, Administrative Patent Judges.
BRANCH, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1-9 and 12-18, which are all of the claims pending in the application.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Technology
The application relates to specifying packet address range
cacheability. Spec. Abstract.
1 According to Appellant, the real party in interest is Avaya, Inc. App. Br. 2.
Appeal 2018-002486
Application 14/041, 7 51
Illustrative Claim
Claim 1 is illustrative and reproduced below:
1. A method for specifying packet address range
cacheability, the method comprising the steps of:
receiving a memory allocation request from an application
running on a network element configured to implement packet
forwarding operations, by an operating system of the network
element, the memory allocation request including a table ID
associated with one of several packet address tables associated
with the application, the one of several packet address tables to
be stored using the memory allocation;
wherein the network element comprises a forwarding
plane and a control plane;
allocating a memory address range by the operating
system to the application in response to the memory allocation
request;
storing the one of several packet address tables in a first
memory associated with the control plane and a second memory
associated with the forwarding plane, wherein the one of several
packet address tables comprises entries populated by the control
plane and used by the forwarding plane to implement packet
forwarding decisions; and
inserting, by the operating system, an entry in a
cacheability register containing entries specifying cacheability of
memory address ranges based on table IDs, the entry including
the table ID of the one of several packet address tables associated
with the application, the memory address range allocated in
response to the memory allocation request, and a cacheability
indicator of the allocated memory address range.
2
Appeal 2018-002486
Application 14/041, 7 51
References and Re} ections2
Claims 1-9 stand rejected under U.S.C. § 103 as unpatentable over
Archer et al. (US 2010/0191923 Al; published July 29, 2010) ("Archer"),
Anthony et al. (US 4,885,680; Dec. 5, 1989) ("Anthony"), "Multilevel
Paging," (March 6, 1998; available at
http://dysphoria.net/ OperatingSystemsl/ 4_mul tilevel_paging .html)
("Dysphoria.net"), and Applicant Admitted Prior Art. Final Act. 4--13.
Claims 12-16 stand rejected under 35 U.S.C. § 103 as unpatentable
over Archer, Anthony, Dysphoria.net, Applicant Admitted Prior Art, and
Vankatachary et al. (US 2004/0249803 Al; published Dec. 9, 2004)
("Vankatachary"). Final Act. 13-21.
Claim 17 stands rejected under 35 U.S.C. § 103 as unpatentable over
Archer, Anthony, Dysphoria.net, Applicant Admitted Prior Art,
Vankatachary, and Ward et al. (US 2012/0044947 Al; published Feb. 23,
2012) ("Ward"). Final Act. 21-22.
Claim 18 stands rejected under 35 U.S.C. § 103 as unpatentable over
Archer, Anthony, Dysphoria.net, Applicant Admitted Prior Art, and Ward.
Final Act. 22-23.
2 Rather than repeat the Examiner's positions and Appellant's arguments in
their entirety, we refer to the above mentioned Appeal Brief filed August 30,
2017 ("App. Br."), as well as the following documents for their respective
details: the Final Rejection mailed March 30, 2017 ("Final Act."), the
Examiner's Answer mailed November 3, 2017 ("Ans."), and Appellant's
Reply Brief filed January 2, 2018 ("Reply Br.").
3
Appeal 2018-002486
Application 14/041, 7 51
ANALYSIS 3
We have reviewed the Examiner's rejections in light of Appellant's
arguments. We have considered in this Decision only those arguments
Appellant actually raised in the Briefs. Any other arguments Appellant
could have made but chose not to make in the Briefs are deemed to be
waived. See 37 C.F.R. § 4I.37(c)(l)(iv). We adopt the Examiner's findings
and conclusions as our own, to the extent consistent with our analysis herein.
Appellant argues that "it is inconsistent to recognize a virtual memory
page table in one reference (Archer et al.) as being one claim element (the
cacheability register) and a virtual memory page table in a second reference
(dysphoria) as being an entirely different claim element (packet address
table)." Appellant contends that "the virtual memory page table structure
from the two references is not two different claim elements" and that "the
page table structure of Anthony et al. is also considered equivalent to the
cacheability register rather than the packet address table." Based on the
foregoing, Appellant contends that "if the disclosures of virtual memory
page tables in the references are treated consistently, the combination of
Archer et al. and dysphoria does not teach or suggest both the cacheability
register and the packet address table of claim 1." App. Br. 12-13; Reply
Br. 4--5.
3 Appellant argues claims 1-9 collectively with reference to claim 1. App.
Br. 10-16. See Reply Br. 4--6. Appellant argues the remaining claims with
reference to the arguments presented with respect to claim 1, adding only
that the additional references do not remedy the shortcomings. App. Br. 16-
17. Accordingly, our Decision turns on our analysis of claim 1, and, except
for our ultimate Decision, we do not mention the additional claims.
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Appeal 2018-002486
Application 14/041, 7 51
We find this argument unpersuasive of error. Appellant has not
persuasively established that the claim limitations fail to read on the
teachings for which these elements are cited. Whether two claim elements
map to identical elements in two different references is not an argument
against patentability if the claim limitations otherwise read on the cited
elements. We know of no controlling law that dictates otherwise.
Moreover, Appellant does not persuasively rebut the Examiner's response to
Appellant's arguments. Reply Br. 4--5; Ans. 22-23.
Appellant also argues that Dysphoria.net does not disclose "the
memory allocation request including a table ID associated with one of
several packet address tables associated with the application, the one of
several packet address tables to be stored using the memory allocation."
App. Br. 13-14.
We find this argument unpersuasive of error. Rather, we are
persuaded by the Examiner that "[ w ]hen combined with the teachings of
Archer, Archer and Dysphoria.net disclose the allocation request (Archer),
inserting an index in the first table (Archer), and using the index in the first
table to look up a second table that holds addresses (Dysphoria.net)." Ans.
24. Appellant does not persuasively rebut the Examiner's response to
Appellant's argument in this regard. See generally Reply Br.
Appellant also argues that "one of ordinary skill would not have found
it obvious to modify features analogous to a cacheability register in one
reference to include attributes of a packet address table, from another
reference, used to implement packet forwarding decision in the forwarding
plane of a network element." App. Br. 15. See Reply Br. 5---6.
5
Appeal 2018-002486
Application 14/041, 7 51
Appellant's argument is unpersuasive of error at least because it does
not address the Examiner's reasons for combining, namely to "enable the
network element to use a caching scheme that improves system performance
as a result of reduced memory latency and improved coherence of data."
Final Act. 9 (citing Anthony col. 2, 11. 35-39).
In view of the foregoing, we are not persuaded of error in the
Examiner's rejection of claim 1.
DECISION
For the reasons above, we affirm the Examiner's decision rejecting
claims 1-9 and 12-18.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(±).
AFFIRMED
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