ARM LIMITED

Patent Trials and Appeals Board

Nov 19, 2021

2020003224 (P.T.A.B. Nov. 19, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/952,807 11/25/2015 Michael John WILLIAMS JRL-550-1916 2378
73459 7590 11/19/2021
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
DOMAN, SHAWN
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
11/19/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MICHAEL JOHN WILLIAMS,
RICHARD ROY GRISENTHWAITE, and SIMON JOHN CRASKE
____________

Appeal 2020-003224
Application 14/952,807
Technology Center 2100
____________

Before JEREMY J. CURCURI, NATHAN A. ENGELS, and
AMEE A. SHAH, Administrative Patent Judges.

SHAH, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), the Appellant1 appeals from the
Examiner’s final decision to reject claims 1–3 and 5–19. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. The Appellant identifies the real party in interest as ARM
Limited. Appeal Br. 3.
Appeal 2020-003224
Application 14/952,807

2
CLAIMED SUBJECT MATTER
The Appellant’s invention “relates to data processing. More
particularly, it relates to handling system errors in a data processing
apparatus.” Spec. 2, ll. 4–5.
Claims 1 and 19 are the independent claims on appeal. Claim 1 is
illustrative of the subject matter on appeal and is reproduced below:
1. Apparatus for data processing comprising:
processing circuitry to perform data processing operations
in response to data processing instructions, to determine if an
error memory barrier condition exists and to perform an error
memory barrier procedure in dependence on whether the error
memory barrier condition exists, the error memory barrier
condition indicating that the error memory barrier procedure will
be carried out in response to an error exception condition,
wherein the processing circuitry is capable of setting the error
exception condition in a first register location upon detection that
a data processing operation has not been successful,
wherein the error memory barrier procedure comprises, if
the error exception condition is set and if an error mask condition
is set:
setting a deferred error exception condition in a
second register location; and
clearing the error exception condition in the first
register location, and
wherein the processing circuitry is capable of determining
that the error memory barrier condition exists in response to an
error memory barrier instruction in the data processing
instructions.
Appeal Br. 18 (Claims App.).

Appeal 2020-003224
Application 14/952,807

3
REFERENCES
The prior art references relied upon by the Examiner are:
Name Reference Date
Col et al. (“Col”) US 5,887,175 Mar. 23, 1999
Brauch US 6,173,248 B1 Jan. 9, 2001
Grisenthwaite et al.
(“Grisenthwaite”)
US 2011/0231633 A1 Sept. 22, 2011
“ARM CortexTM-M Programming Guide to Memory Barrier Instructions,”
Application Note 321, ARM Limited, 2012 (“ARM”)

REJECTIONS
Claims 1–3, 5–14, and 19 stand rejected under 35 U.S.C. § 103 as
unpatentable over Brauch, ARM, and Col.
Claims 15–18 stand rejected under 35 U.S.C. § 103 as unpatentable
over Brauch, ARM, Col, and Grisenthwaite.

OPINION
The Examiner relies on the combination of Brauch, ARM, and Col for
teaching the limitations of independent claim 1. Specifically, the Examiner
finds that Brauch teaches “an apparatus for data processing comprising:
processing circuitry to perform data processing operations in response to
data processing instructions,” a procedure that will be carried out in response
to an error exception condition, the circuitry “capable of setting an error
exception condition . . . upon detection that a data processing operation has
not been successful,” setting a deferred error exception condition in a
register, and clearing the error exception condition. Final Act. 2–3. The
Examiner relies on ARM for teaching “determining if an error memory
barrier condition exists and performing an error memory barrier procedure in
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Application 14/952,807

4
dependence on whether the error memory barrier condition exists,” “the
error memory barrier condition indicat[ing] the error memory barrier
procedure,” the error memory barrier comprising setting the deferred error
exception condition and clearing the error exception condition, and “wherein
the processing circuitry is capable of determining that the error memory
barrier condition exists in response to an error memory barrier instruction in
the data processing instructions.” Id. at 3–4. The Examiner relies on Col to
teach “a second location,” i.e., “using separate registers for indicating an
exception has been detected and indicating that an exception is deferred.”
Ans. 4–5; see also Final Act. 4.
The Appellant argues that “neither Brauch nor Col describes setting
(and clearing) an error exception condition in a first register and setting a
deferred error exception condition in a different register, as required by
claim 1,” and that ARM does not cure this deficiency. Appeal Br. 10; see
also id. at 8–9. The problem with this argument is that it is an argument
against Brauch and Col separately when the Examiner relies on the
combination of the references to teach the setting and clearing limitations.
The test for obviousness is not what any one reference would have
suggested, but rather what the combined teachings of the references would
have suggested to those of ordinary skill in the art. See In re Keller, 642
F.2d 413, 426 (CCPA 1981). “[O]ne cannot show non-obviousness by
attacking references individually where, as here, the rejection[ is] based on
combinations of [the] references.” Id. (citation omitted).
Here, the Examiner finds that Brauch teaches “the claimed setting and
clearing an error exception condition” and “setting a deferred error
condition, which is simply setting a bit indicating that there is a deferred
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Application 14/952,807

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exception pending,” findings which the Appellant does not contest. Ans. 4;
see also Appeal Br. 8–10. The Examiner acknowledges that Brauch teaches
“using a single location in which a 0 logic state indicates that an exception
has been detected and a 1 logic state indicates a deferred exception is
pending,” as highlighted by the Appellant. Ans. 4; see also Appeal Br. 10.
“Given that Brauch discloses a single value, or register location, the
Examiner cites Col as a secondary reference teaching a second location.”
Ans. 4. Specifically, the Examiner finds that “the location in Brauch could
be used exclusively for indicating when an exception is deferred, with a
separate location used for indicating an exception has been detected, as
taught by Col.” Id.; see also id. at 5 (citing Col, col. 4, ll. 24–34, col. 5,
ll. 1–10, 66–67).
The Appellant argues that the Examiner “appears to equate Col’s error
flag to the claimed error exception condition and to equate Col’s interrupt
flag to the claimed deferred exception condition. However, Col’s interrupt
flag cannot reasonably be mapped onto the claimed deferred error exception
condition.” Reply Br. 2. Specifically, the Appellant argues “[t]he claimed
deferred error exception condition requires the error exception condition to
have been set, which is not true of Col’s interrupt flag.” Id. at 2–3.
However, the Examiner relies on the combination of Brauch and ARM for
teaching the circuitry capable of setting the error exception condition in a
first location, i.e., “[t]he claimed deferred error exception condition [that]
requires the error exception condition to have been set” (Reply Br. 2–3) and
carrying out a procedure comprising “if the error exception condition is set
and if an error mask condition is set: setting a deferred error exception
condition in a . . . register location; and clearing the error exception
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condition in the first register location.” See Final Act. 2–3. The Examiner
relies on Col only for teaching the use of a separate location for setting the
deferred error exception condition as taught by Brauch and ARM. See
Ans. 5. The Examiner is not equating Col’s interrupt flag with the “claimed
deferred error exception” (Reply Br. 2); rather, the Examiner explains that
Col’s control register having an interrupt flag that indicates “whether the
exception should be handled or deferred” and Col’s error flag resister having
an error flag “that indicates an exception has occurred” would be combined
with Brauch’s setting and clearing of an error exception condition in a first
register location and setting of a deferred error condition exception to teach
the claimed “setting a deferred error exception condition in a second register
location; and clearing the error exception condition in the first register
location.” See Ans. 5.
The Appellant’s arguments that “neither Brauch nor Col describes
setting (and clearing) an error exception condition in a first register and
setting a deferred error exception condition in a different register, as
required by claim 1” (Appeal Br. 10) and “Col also does not describe setting
and clearing an error exception condition in a first register location and
setting a deferred error exception condition in a second register
location” (Reply Br. 3) are unpersuasive because these arguments do not
address or explain why the combination does not teach the limitations. To
the extent the Appellant argues that the combination does not teach “the
setting (and clearing) an error exception condition in a different register to a
register in which a deferred error exception is set” (Appeal Br. 11), we
disagree. As discussed above, the Examiner finds Brauch teaches
processing circuitry capable of setting and clearing an error exception
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condition and setting a deferred error condition exception in disclosing
“using a single location in which a 0 logic state indicates that an exception
has been detected and a 1 logic state indicates a deferred exception is
pending.” Ans. 4; Appeal Br. 10. The Examiner relies on Col for teaching
using different registers for doing so. See Ans. 4–6.
We are further not persuaded of error by the Appellant’s arguments
that “The Brauch-ARM-Col combination fails to teach or suggest an EMB
condition and an EMB procedure, as recited in claim 1” (Appeal Br. 12
(emphasis omitted); see also id. at 13–14) and “The Brauch-ARM-Col
combination fails to teach or suggest an EMB procedure will be carried out
in response to an error exception condition, as recited in claim 1” (id. at 14
(emphasis omitted); see also id. at 15). Rather, we agree with and adopt the
Examiner’s findings and interpretations as presented in the Answer at
pages 6 through 8. For the reasons discussed above, we also find
unpersuasive of error the Appellant’s argument that
as described above, Brauch, ARM and Col do not disclose setting
and clearing an error exception condition in a first register
location and setting a deferred error exception condition in a
second register location, as required by the claimed error
memory barrier procedure. Therefore, the claimed error memory
barrier procedure is not disclosed by any of Brauch, ARM and
Col or their combination.
Reply Br. 3–4 (emphasis omitted); see also Appeal Br. 12–13.
Thus, we sustain the Examiner’s rejection under 35 U.S.C. § 103 of
independent claim 1, of dependent claims 2, 3, and 5–14, and of independent
claim 19, for which the Appellant relies on the arguments presented for
claim 1. See Appeal Br. 7, 15. We also sustain the Examiner’s rejection
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8
under 35 U.S.C. § 103 of claims 15–18, for which the Appellant relies on the
arguments presented for the rejection of claim 1. See Appeal Br. 16.
CONCLUSION
The Examiner’s decision to reject claims 1–3 and 5–19 is sustained.
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/ Basis Affirmed Reversed
1–3, 5–14, 19 103 Brauch, ARM, Col 1–3, 5–14,
19

15–18 103 Brauch, ARM, Col,
Grisenthwaite
15–18
Overall
Outcome
1–3, 5–19

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).

AFFIRMED