Ex Parte LaBerge

Board of Patent Appeals and Interferences

Aug 28, 2009

10838511 (B.P.A.I. Aug. 28, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte PAUL A. LABERGE
____________________

Appeal 2008-005230
Application 10/838,511
Technology Center 2100
____________________

Decided: August 31, 2009
____________________

Before JEAN R. HOMERE, JOHN A. JEFFERY, and JAMES R. HUGHES,
Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 27-42. Claims 1-26 have been canceled. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Appellant’s Invention
Appellant invented a computer system including a bridge for
establishing communication between different buses. In particular, the
bridge bypasses a memory bus interface, capturing read data directly into a
buffer of the local bus. (Spec. 4, ll. 2-23.)1

Claim
Independent claim 27 further illustrates the invention. It reads as
follows:
27. A computer system comprising:
a local bus;
a memory bus capable of indicating data and a strobe
signal; and
a bridge comprising:
communication lines to communicate the data and
the strobe signal from the memory bus to a region closer to the
local bus than to the memory bus, and

1 We refer to Appellant’s Specification (“Spec.”), Second Amended Appeal
Brief (“App. Br.”) filed November 20, 2007, and Reply Brief (“Reply Br.”)
filed April 14, 2008. We also refer to the Examiner’s Answer (“Ans.”)
mailed February 13, 2008.
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a buffer to respond directly to the strobe signal in
the region to capture the data from the communication lines.

References
The Examiner relies on the following references as evidence of
unpatentability:
Andrade US 5,623,638 Apr. 22, 1997

Derrick US 5,906,659 May 25, 1999

Rejections
The Examiner rejects claims 27-31, 33-37, and 39-41 under 35 U.S.C.
§ 102(b) as anticipated by Andrade.
The Examiner rejects claims 32, 38, and 42 under 35 U.S.C. § 103(a)
as unpatentable over Andrade and Derrick.

Appellant’s Contentions
Appellant contends that the Examiner improperly rejected the claims.
Specifically, Appellant contends that the invention of independent claims 27,
33, and 39 (and dependent claims 28-31, 34-37, 40, and 41) is not
anticipated by Andrade because the reference does not disclose, teach, or
suggest communicating data and a strobe signal (e.g., through
communication lines) from a memory bus to a region closer to the local bus
than to the memory bus. (App. Br. 8-12; Reply Br. 2-9.) Appellant also
contends that the Examiner failed to establish a proper prima facie case of
obviousness for claims 32, 38, and 42 because “the Derrick reference does
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not obviate the deficiencies of the Andrade reference” and “does not teach or
even suggest, either explicitly, implicitly, or inherently, communication lines
to communicate data and a strobe signal from a memory bus to a region
closer to a local bus than to the memory bus.” (App. Br. 14-15 (emphasis
omitted).)

Examiner’s Findings and Conclusions
The Examiner finds that Andrade discloses each feature of
Appellant’s claimed invention (as claimed in claims 27-31, 33-37, and 39-
41). (Ans. 3-10, 13-18.) In particular, the Examiner finds that Andrade
discloses communicating data and a strobe signal through communication
lines from a memory bus to a buffer in a region closer to the local bus than
to the memory bus. (Ans. 4, 14-17.) The Examiner also finds that Andrade
and Derrick teach each feature of Appellant’s claims 32, 38, and 42. (Ans.
10-12.) The Examiner provides a rationale for the reference combination as
required by 35 U.S.C. § 103(a), and determined that it would have been
obvious for one of skill in the art to combine the references. (Ans. 12.)

ISSUES
Based on Appellant’s contentions, as well as the findings and
conclusions of the Examiner, the issue before us is as follows:
Did Appellant establish that the Examiner erred in determining that
Andrade discloses communicating data and a strobe signal through
communication lines from a memory bus to a buffer in a region closer to the
local bus than to the memory bus?
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FINDINGS OF FACT (FF)
We find that the following enumerated findings are relevant to the
rejections under review and are supported by at least a preponderance of the
evidence. Ethicon, Inc. v. Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988)
(explaining the general evidentiary standard for proceedings before the
Office).

Appellant’s Invention
1. Appellant claims a computer system including a bridge having
communication lines to communicate data and a strobe signal from a
memory bus to a buffer in a region closer to the local bus than to the
memory bus. (App. Br. 4.) Appellant’s Specification explains:
Unlike conventional bridges, the bridge 34 bypasses a memory
bus interface 64 (of the bridge 34) and captures the read data
directly into the buffer 42 of the local bus interface 60.

. . . the bridge 34 effectively extends the memory channel
provided by the memory bus 41 inside the bridge 34. In this
manner, the data and strobe lines of the memory bus 41 (via
internal data and data strobe conductive traces, or lines 80) are
effectively extended by placing the buffer 42 closer to the local
bus 33 than to the memory bus 41.

(Spec. 4, ll. 14-20; Figs. 6, 7.)

Andrade Reference
2. Andrade describes a memory control unit (MCU) for
minimizing delay in dynamic random access memory (DRAM) control
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signal timing. (Col. 1, ll. 10-19.) Andrade discloses a CPU local bus
connecting a CPU to the MCU and a memory bus connecting a DRAM
memory array to the MCU. (Col. 6, ll. 44-47, 60-62; col. 7, ll. 6-11; Figs. 1,
2 (element 165), 5 (element 90).)
3. Andrade’s MCU establishes communication between the
memory and local buses, i.e., acts as a bridge between the buses. (Col. 2, l.
28 to col. 3, l. 16; col. 7, ll. 37-50.)
4. Andrade’s MCU includes a CPU local bus interface, a data
control buffer, and a memory bus interface. (Col. 7, ll. 37-61; col. 8, ll. 21-
33; Fig. 2, elements 40, 65, 68.)
5. Andrade describes constructing the CPU local bus interface and
the data control buffer as a single unit, i.e., merging the local bus interface
and data control buffer eliminating the interconnecting data lines. (Col. 8, ll.
30-33; Fig. 2, elements 40, 68.)
6. Andrade describes a basic memory transaction and memory
data cycle. (Col. 11, ll. 4-18.) Memory data transfer begins during bus
cycle T1 and becomes available (to the local bus and CPU) during bus cycle
T2. The data is latched (in the buffer) at the end of the T2 cycle. (Col. 11,
ll. 4-18; Figs. 2 (element 68), 6A-6E, 7A, 7B.)

PRINCIPLES OF LAW
Burden on Appeal
Appellant has the burden on appeal to the Board to demonstrate error
in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir.
2006) (“On appeal to the Board, an applicant can overcome a rejection by
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showing insufficient evidence of prima facie obviousness or by rebutting the
prima facie case with evidence of secondary indicia of nonobviousness.”)
(quoting In re Rouffet, 149 F.3d 1350, 1355 (Fed.Cir. 1998)).

Anticipation
Anticipation is a question of fact. In re Schreiber, 128 F.3d 1473,
1477 (Fed. Cir. 1997). Under 35 U.S.C. § 102, “[a] claim is anticipated only
if each and every element as set forth in the claim is found, either expressly
or inherently described, in a single prior art reference.” Verdegaal Bros.,
Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987); see also
Perricone v. Medicis Pharm. Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005).

ANALYSIS
Initially, we note the following claim groupings and waiver issues.
Appellant briefly contends that the Examiner failed to establish a proper
prima facie case of obviousness for claims 32, 38, and 42, restating the
arguments made with respect to claims 27, 33, and 39, as well as the
Andrade reference – that “the Derrick reference does not obviate the
deficiencies of the Andrade reference” and does not teach or suggest
“communication lines to communicate data and a strobe signal from a
memory bus to a region closer to a local bus than to the memory bus.”
(App. Br. 14-15 (emphasis omitted).) However, this statement is insufficient
to rise to the level of a separate argument requiring our consideration. See
Hyatt v. Dudas, 551 F.3d 1307, 1314 (Fed. Cir 2008) (“When the appellant
fails to contest a ground of rejection to the Board, section 1.192(c)(7) [(now
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section 41.37(c)(1)(vii))] imposes no burden on the Board to consider the
merits of that ground of rejection. . . . [T]he Board may treat any argument
with respect to that ground of rejection as waived.”); see also In re Guess,
2009 WL 1598475 at *1 (Fed. Cir. June 9, 2009) (“Appellants failed to
argue that any limitations unique to [the claims] survive [the rejection].
Appellants have therefore waived any such arguments on appeal.”) (citing In
re Watts, 354 F.3d 1362, 1367 (Fed. Cir. 2004)).
We find that Appellant argues the merits of only independent claims
27, 33, and 39. We will, therefore, treat dependent claims 28-32 as standing
or falling with independent claim 27, dependent claims 34-38 as standing or
falling with independent claim 33, and dependent claims 40-42 as standing
or falling with independent claim 39. We accept Appellant’s grouping of the
claims. See 37 C.F.R. § 41.37(c)(1)(vii) (“Notwithstanding any other
provision of this paragraph, the failure of appellant to separately argue
claims which appellant has grouped together shall constitute a waiver of any
argument that the Board must consider the patentability of any grouped
claim separately.”). Accordingly, we address only those arguments that
Appellant presents in the Briefs. Arguments that Appellant could have made
but chose not to make in the Briefs are waived.

Rejection of the Claims under 35 U.S.C. § 102(b)
We decide the question of whether Appellant establishes the
Examiner erred in determining Andrade discloses communicating data and a
strobe signal through communication lines from a memory bus to a buffer in
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a region closer to the local bus than to the memory bus. We will affirm the
Examiner’s rejection of claims 27-42 for the reasons that follow.
We initially note disagreement between the Examiner and the
Appellant concerning the definition of “closer,” and in particular, “a region
closer to the local bus than to the memory bus.” (App. Br. 8-10; Reply Br.
2-8; Ans. 4, 13.) We determine the scope of the claims in patent
applications not solely based on the claim language, but upon giving claims
“their broadest reasonable interpretation consistent with the specification”
and “in light of the specification as it would be interpreted by one of
ordinary skill in the art.” In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359,
1364 (Fed. Cir. 2004) (citations omitted). Appellant does not define the
term “closer” in the Specification. Appellant’s disclosure provides only
limited support for the claimed feature – the region (buffer) being closer to
the local bus than the memory bus – describing the memory data lines (and
strobe line) of the memory bus directly connected to the buffer in the local
bus interface (rather than being connected through an intervening buffer in
the memory bus interface). (FF 1.)
Accordingly, we give the term “closer” and the limitation “a region
closer to the local bus than to the memory bus” their broadest reasonable
interpretation, and find that: (1) “closer” would be commonly understood to
mean physically closer, and (2) the limitation “a region [buffer] closer to the
local bus than to the memory bus” would be commonly understood to mean
that the memory data lines (and strobe line) of the memory bus terminate at
a location (in a buffer) physically closer to the local bus than the memory
bus. This interpretation is consistent with Appellant’s Specification, and is
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synonymous with (although not exactly the same as) both “spatially closer”
and “electrically closer” as discussed by the Appellant and the Examiner.
We find unpersuasive Appellant’s contention that Andrade does not
disclose communicating data and a strobe signal through communication
lines from a memory bus to a buffer (physically) closer to the local bus than
to the memory bus. Andrade describes a memory control unit (MCU)
connected to a CPU local bus and a memory bus. The MCU is a bridge.
The MCU/bridge includes a CPU local bus interface, a data control buffer,
and a memory bus interface. (FF 2-4.) Andrade explicitly discloses one of
skill in the art constructing the CPU local bus interface and the data control
buffer as a single unit, i.e., merging the local bus interface and data control
buffer eliminating the interconnecting data lines. (FF 5.) Thus, we find that
Andrade discloses connecting the data lines of the memory bus to the data
control buffer which is part of the local bus interface connected directly to
the local bus (by a bus stub).
Andrade discloses the memory lines bypassing the memory bus
interface. The memory lines terminate in the data control buffer, bypassing
the intervening memory bus interface. (FF 5.) Accordingly, we find the
data control buffer is necessarily physically closer to the local bus than the
memory bus, which is separated from the data control buffer by the memory
bus interface. We note that Appellant’s disclosure of this feature – the
memory data lines (and strobe line) of the memory bus bypassing the
memory bus interface and terminating in a buffer physically closer to the
local bus than the memory bus (FF 1; Spec., Figs. 6, 7) – is commensurate
with that of Andrade. While the disclosures lack detail, specifically the
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actual dimensions of the regions in question, locating the buffer and memory
lines as described is well within the skill of one knowledgeable in chip
(integrated circuit) design. Both disclosures are enabling to one of skill in
the art.
We also note, as did the Examiner (Ans. 15), that Andrade does not
explicitly describe a strobe signal (strobe signal line) for latching the data in
the buffer. Andrade does, however, latching data in the buffer at the end of
bus cycle T2. (FF 6.) Accordingly, as explained by the Examiner, one of
skill in the art would understand that latching the data would require a
memory strobe (control) signal and corresponding signal line.
The Examiner properly explains where each feature of Appellant’s
claims 27, 33, and 39 are shown in the Andrade reference. Accordingly, we
find Andrade discloses each feature of Appellant’s claims 27, 33, and 39,
anticipating the claims. Appellant provides no persuasive evidence
supporting his assertions to contrary, and has not met the burden to show
reversible error in the Examiner’s finding that Andrade discloses
communicating data and a strobe signal through communication lines from a
memory bus to a buffer in a region closer to the local bus than to the
memory bus. For all the reasons noted above, we will sustain the
Examiner’s rejection of claims 27, 33, and 39 (and claims 28-32, 34-38, and
40-42).

CONCLUSION OF LAW
On the record before us, we find Appellant has not established that the
Examiner erred in determining Andrade discloses each feature of
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Appellant’s invention, in particular, communicating data and a strobe signal
through communication lines from a memory bus to a buffer in a region
closer to the local bus than to the memory bus.

DECISION
We affirm the Examiner's rejection of claims 27-31, 33-37, and 39-41
under 35 U.S.C. § 102(b).
We affirm the Examiner's rejection of claims 32, 38, and 42 under 35
U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED

msc

Fletcher Yoder (Micron Technology, Inc.)
P.O. Box 692289
Houston, TX 77269-2289