Ex Parte Flynn et al

Board of Patent Appeals and Interferences

May 12, 2010

10347481 (B.P.A.I. May. 12, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DAVID W. FLYNN, DAVID J. SEAL,
WILCO DIJKSTRA, and MICHAEL R. NONWEILER
____________________

Appeal 2009-46101
Application 10/347,481
Technology Center 2100
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Decided: May 12, 2010
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Before JOHN A. JEFFERY, LEE E. BARRETT, and JEAN R. HOMERE,
Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1 Filed January 21, 2003. The real party in interest is ARM Limited. An oral
hearing was held in this appeal on May 4, 2010.
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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s final rejection of claims 1 through 15, 17 through 33 and 35
through 37. Claims 16, 34 and 38 have been cancelled. (Br. 2.) We have
jurisdiction under 35 U.S.C. § 6(b) (2008).
We reverse.
Appellants’ Invention
Appellants invented a method and data processing apparatus for
swapping data values. (Spec. 1, ll. 3-4.) As shown in Figure 5 of
Appellants’ drawings, the data processing apparatus includes a data
processing unit (530) for executing a sequence of instructions to perform an
arithmetic operation (550) and a logical operation (560). (Spec. 18, ll. 11-
25.) The data processing apparatus further includes a plurality of registers
(540) that store data words, which the data processing unit (530) accesses
when executing the sequence of instructions. (Id.) In particular, upon
receiving within the instruction sequence an endian reverse instruction
specifying a source register (205) and a destination register (215) in the
plurality of registers (540), the data processing unit (530) treats each input
data word as a plurality of independent sections, each including a plurality of
data values that are subsequently swapped independently within each
section. (Spec. 1-9.)
Illustrative Claim
Independent claim 1 is further illustrates the invention. It reads as
follows:
1. A data processing apparatus, comprising:

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a data processing unit for executing a sequence of
instructions for performing at least one arithmetic operation and
at least one logical operation;

a plurality of registers for storing data words for access
by the data processing unit when executing said sequence of
instructions;

the data processing unit, responsive to an endian reverse
instruction within said sequence specifying a source register
and a destination register in said plurality of registers, for
applying an endian reverse operation to an input data word Rm
stored in said source register, the input data word comprising a
plurality of data values, wherein said endian reverse operation
yields a result data word Rd for storing in said destination
register, the result data word given by:

treating the input data word as consisting of a
plurality of input sections, the result data word having a
corresponding plurality of result sections, at least one
input section comprising a plurality of data values; and

for at least one of the input sections comprising a
plurality of data values, performing an independent swap
operation on the data values within that input section to form
the result data word Rd in which the corresponding result
section has its data values swapped with respect to that input
section.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Tanaka 5,550,987 Aug. 27, 1996
Witt 5,796,973 Aug. 18, 1998
Witt (‘468) 5,946,468 Aug. 31, 1999
Nguyen US 6,772,244 B2 Aug. 3, 2004
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David A. Patterson and John L. Hennessy, “Computer Organization &
Design, The Hardware Software Interface”, Second Edition, Morgan
Kaufmann Publishers, Inc., 1998. (Hennessy)

Rejections on Appeal
The Examiner rejects the claims on appeal as follows:
1. Claims 1 through 8, 15, 17, 18, 19 through 26, 33, 35, and 36
stand rejected as being unpatentable under 35 U.S.C. § 103(a) over the
combination of Tanaka and Hennessy.
2. Claims 9 through 14, 22, 28 through 32 stand rejected as being
unpatentable under 35 U.S.C. § 103(a) over the combination of Tanaka,
Hennessy, and Witt.
3. Claims 37 and 38 stand rejected as being unpatentable under
35 U.S.C. § 103(a) over the combination of Tanaka, Hennessy, and Nguyen.

Appellants’ Contentions
Appellants contend that Tanaka and Hennessy are not properly
combined, and that the proffered combination does not teach or suggest a
data processing unit executing sequence of instructions to perform an
arithmetic operation and a logical operation, whereupon receiving within the
sequence of instructions an endian reverse instruction specifying a source
register and a destination register from a plurality of registers containing a
data word, the data processing unit independently swaps the values in each
data word. (Br. 9-20, Reply Br. 9-12.) According to Appellants, while
Tanaka discloses a data transfer device that uses an endianness reversing
block to perform an endian reverse operation on the data as it passes
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between two buses, the reference does not teach the sequence of instructions
including an endian reverse instruction that specifies the source and
destination registers. (Id.) Further, Appellants argue that the Examiner
failed to provide a rational underpinning to support his legal conclusion of
obviousness. (Br. 19.) Additionally, Appellants argue that Tanaka teaches
away from the claimed invention since Tanaka provides a separate logic to
convert data into an endian format. (Id.) Last, Appellants argue that the
secondary references do not cure the deficiencies of Tanaka, and that there is
insufficient rationale for the proffered combination. (Id. at 20-23.)

Examiner’s Findings
The Examiner finds the combination of Tanaka’s CPU, data transfer
device and the first bus system teaches the claimed data processing unit.
(Ans. 4.) In particular, the Examiner finds Tanaka’s processing unit
includes a plurality of registers, and can perform arithmetic and logical
operations upon receiving a plurality of instructions since such devices and
operations are inherent to all processors, as evidenced by Hennessy’s
disclosure. (Id. at 16-19.) Further, the Examiner finds that Tanaka discloses
a plurality of swap instruction signals for performing endian reverse
operations on data word stored in the register. (Id. at 20.) The Examiner
subsequently concludes the disclosures of Tanaka and Hennessy are properly
combined to render the claim unpatentable. (Id. at 20-21.)

II. ISSUE
Have Appellants shown that the Examiner erred in finding that
Tanaka and Hennessy are properly combined to teach or suggest a data
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processing unit receiving within a sequence of instructions an endian reverse
instruction specifying a source register and a destination register, as recited
in independent claim 1?

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Tanaka
1. As shown in Figure 2, Tanaka discloses a data transfer device
(1) for transferring data between a first memory (5) coupled to a CPU (4) via
a first bus system (2) and a second memory (6) coupled to the data transfer
device via a second system bus (3). (Col. 1, ll. 5-10, col. 5, ll. 48-58.)
2. The data transfer device (1) includes a swap control section (13,
14) for swapping a data word upon receiving a swap instruction set in the
register where the word is stored. (Col. 1, ll. 61-64, col. 6, ll. 4-48.)
3. The data transfer device (1) also includes a data structure
storage circuit control (16) for storing transferred data values. It further
contains an input endian storage circuit (17) and an output endian storage
circuit (18) for storing values that the input circuit (11) handled. (Col. 6, ll.
60-67.) The CPU sets the data structure values of these storage devices and
registers. (Col. 7, ll. 11-15.)
4. The data transfer device (1) additionally includes a control
circuit (10) that issues a sequence of instructions including (1) a read request
to the control circuit (11) (col. 5, ll. 59-60;) (2) a selection instruction to the
selection circuit (12) to select an output from the swap circuit (14) (col. 5, l.
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66- col. 6, l. 3, col. 8, ll. 26-35, col. 8, ll. 26-35,) and (3) a swap instruction
to the swap control section (13, 14) (col. 11, ll. 43-49, col. 12, ll. 17-21.)
IV. PRINCIPLES OF LAW
“On appeal to the Board, an applicant can overcome a rejection [under
§ 103] by showing insufficient evidence of prima facie obviousness or by
rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.” In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)
(citation omitted).
V. ANALYSIS
Independent claim 1 requires, inter alia, a data processing unit
receiving within a sequence of instructions an endian reverse instruction
specifying a source register and a destination register. (Br. 13, Claims
App’x.)
As set forth in the Findings of Fact section, Tanaka discloses a data
processing unit that interfaces with a data transfer device containing a
controller that issues a sequence of instructions including a reverse endian
instruction to a swap control section. (FF 1, 2, 4.) Tanaka further discloses
that the data transfer device includes a plurality of registers including a
dedicated register for storing transferred values, a dedicated source endian
register and a dedicated destination endian register. (FF 3.)
We find that Tanaka, at best, teaches or suggests a data processing
unit (the data transfer device) having modules that are configured to issue a
sequence of instructions including a reverse endian instruction to swap data
values, which are stored in a plurality of registers including a source endian
register and a destination endian register. We find, however, that the endian
reverse instruction issued in Tanaka needs not specify the source and
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destination registers where the data values are fetched and transferred
respectively since the location of these dedicated storage devices is static.
Consequently, we find that Tanaka’s disclosure does not teach or suggest the
data processing unit receiving "an endian reverse instruction . . . specifying a
source register and a destination register," i.e., a single instruction specifying
a source and destination registers. We find untenable, for this same reason,
the Examiner’s position that Tanaka’s combination of the CPU coupled to
the data transfer unit teaches the claimed data processing unit. Additionally,
we agree with Appellants that Hennessy does not cure the noted deficiencies
of Tanaka.
Since Appellants have shown at least one error in the rejection of
claim 1, we need not reach the merits of Appellants’ other arguments. It
follows that Appellants have shown that the Examiner erred in concluding
that the combination of Tanaka and Hennessy renders claim 1 unpatentable.
Because claims 2 through 15, 17 through 33 and 35 through 37 also
recite the limitations discussed above, we find that Appellants have also
shown error in the Examiner’s rejection of these claims for the reasons set
forth in our discussion of independent claim 1.

VI. CONCLUSION OF LAW
Appellants have established that the Examiner erred in rejecting
claims 1 through 15, 17 through 33 and 35 through 37as being unpatentable
under 35 U.S.C. § 103(a).

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VII. DECISION
We reverse the Examiner's rejection of claims 1 through 15, 17
through 33 and 35 through 37.

REVERSED

Vsh

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