ARM Limited

Patent Trials and Appeals Board

Nov 2, 2020

15208816 - (D) (P.T.A.B. Nov. 2, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/208,816 07/13/2016 Ali SAIDI P03317US01 8026
134423 7590 11/02/2020
Leveque Intellectual Property Law, P.C.
241 E. 4th Street, #102
Frederick, MD 21701
EXAMINER
WESTBROOK, MICHAEL L
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
11/02/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
eofficeaction@appcoll.com
info@levequeip.com
uspto@levequeip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ALI SAIDI and PRAKASH S. RAMRAKHYANI
____________
Appeal 2019-003342
Application 15/208,816
Technology Center 2100
____________

Before NORMAN H. BEAMER, ADAM J. PYONIN, and
GARTH D. BAER, Administrative Patent Judges.

PYONIN, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s rejection. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Arm Limited as the real party in
interest. Appeal Br. 3.
Appeal 2019-003342
Application 15/208,816

2
STATEMENT OF THE CASE
Introduction
Appellant’s disclosure relates to a cache memory that “has cache
occupancy estimation circuitry to hold a count of insertions of cache lines
into the cache storage for each of the plurality of requesters over a defined
period.” Spec., Abstr. Claims 1, 13, and 14 are independent; claim 1 is
reproduced below for reference (with emphasis added):
1. A cache memory comprising:
cache storage configured to store cache lines for a
plurality of requesters;
cache control circuitry that controls insertion of a cache
line into the cache storage when a memory access request from
one of the plurality of requesters misses in the cache memory;
and
cache occupancy estimation circuitry configured to hold
a count of insertions of cache lines into the cache storage for
each of the plurality of requesters over a defined period.

The Examiner’s Rejections
Claims 1, 2, 6–8, 13, and 14 stand rejected under 35 U.S.C.
§ 102(a)(1) as being anticipated by Gibson (US 2011/0238919 A1; Sept. 29,
2011). Final Act. 3.
Claims 4, 5, and 12 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Gibson and Kornegay (US 7,457,920 B1; Nov. 25, 2008).
Final Act. 8.
Claims 3 and 11 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Gibson and Ramrakhyani (US 2014/0173214 A1; June 19,
2014). Final Act. 10.
Appeal 2019-003342
Application 15/208,816

3
Claims 9 and 10 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Gibson and Evans (US 9,047,225 B1; June 2, 2015).
Final Act. 12.
ANALYSIS
Appellant argues that the Examiner’s anticipation rejection is in error,
because the claimed “cache occupancy estimation circuitry (39) updates the
values it stores, namely a requester ID and an insertion count” (Reply Br. 9;
see Spec. 12:1–9), whereas
Gibson at [¶¶ 57–58] and [¶ 62] and Figure 2 is a management
module which administers table entries in a quota table 240,
where a table entry can include an “occupancy level,” which is
the number of cache lines each group or entity associated with
the ID owns. This occupancy level field, as described in Gibson
at [¶ 62], “. . . can be incremented for the ID owner of the
newly fetched cache data and decremented for the ID of the
victim. . . .”

Reply Br. 9. Appellant illustrates the distinction:
in an example situation in which over a given period a given
owner (starting from zero) has two cache lines allocated and
one victimized. Gibson can only report that the owner then has
one cache line as its “occupancy level”. By contrast, the
present claimed invention only holds onto the allocation
information, so will report that two cache lines have been
allocated for the owner.

Reply Br. 9–10; see also Appeal Br. 11–12, citing Gibson, Fig. 2, ¶¶ 57–58,
62.
“[A]n invention is anticipated if the same device, including all the
claim limitations, is shown in a single prior art reference. Every element of
the claimed invention must be literally present, arranged as in the claim.”
Appeal 2019-003342
Application 15/208,816

4
Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236 (Fed. Cir. 1989).
Appellant’s claim 1 recites a “count of insertions of cache lines.”
We are persuaded by Appellant’s argument. The Examiner finds that
the claimed cache occupancy estimation circuitry configured
to hold a count of insertions of cache lines into the cache
storage for each of the plurality of requesters is equivalent to
Gibson’s Occupancy (Occ) level that indicates the number of
cache lines each group or entity associated with the ID
owns.
Ans. 4. The Examiner further finds that Gibson teaches that the “occupancy
value can be calculated by repeatedly counting a number of cache lines
allocated to the entity offset by a number of cache lines vacated for the
entity.” Ans. 4–5. We agree with Appellant that Gibson counts a net
occupancy level because of the offset for cache lines vacated. See Final Act.
9. The recited “count of insertion lines” is not present in Gibson.
Accordingly, we are constrained by the record to reverse the
Examiner’s anticipation rejection of independent claim1, independent claims
13 and 14 which recite similar limitations, as well as the rejections of the
claims dependent thereon.
DECISION SUMMARY
REVERSED
Claims
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1, 2, 6–8, 13,
14
102(a)(1) Gibson 1, 2, 6–8,
13, 14
4, 5, 12 103 Gibson, Kornegay 4, 5, 12
3, 11 103 Gibson,
Ramrakhyani
3, 11
9, 10 103 Gibson, Evans 9, 10
Overall
Outcome
1–14